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please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 1 post office box 1443 ? houston, texas 772511443 high-performance static cmos technology includes the t320c2xx core cpu object-compatible with the tms320c2xx source-code-compatible with tms320c25 upwardly compatible with tms320c5x 50-ns instruction cycle time commercial and industrial temperature available memory 544 words x 16 bits of on-chip data/program dual-access ram (daram) 8k words x 16 bits of flash eeprom 224k words x 16 bits of total memory address reach ('f243 only) external memory interface ('f243 only) event-manager module eight compare/ pulse-width modulation (pwm) channels two 16-bit general-purpose timers with six modes, including continuous up and up / down counting three 16-bit full compare units with deadband three capture units (two with quadrature encoder-pulse interface capability) single 10-bit analog-to-digital converter (adc) module with 8 multiplexed input channels controller area network (can) module 26 individually programmable, multiplexed general-purpose i / o (gpio) pins six dedicated gpio pins ('f243 only) phase-locked-loop (pll)-based clock module watchdog (wd) timer module serial communications interface (sci) module 16-bit serial peripheral interface (spi) module five external interrupts (power drive protection, reset, nmi, and two maskable interrupts) three power-down modes for low-power operation scan-based emulation development tools available: texas instruments (ti ? ) ansi c compiler, assembler / linker, and c-source debugger full range of emulation products self-emulation (xds510 ? ) third-party digital motor control and fuzzy-logic development support 144-pin qfp pge package ('f243) 68-pin plcc fn package ('f241) 64-pin qfp pg package ('f241) description the tms320f243 and tms320f241 devices are members of the '24x family of digital signal processor (dsp) controllers based on the tms320c2xx generation of 16-bit fixed-point dsps. the 'f243 is a superset of the 'f241. these two devices share similar core and peripherals with some exceptions. for example, the 'f241 does not have an external memory interface. this new family is optimized for digital motor / motion control applications. the dsp controllers combine the enhanced tms320 architectural design of the 'c2xx core cpu for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor / motion control applications. these peripherals include the event manager module, which provides general-purpose timers and pwm registers to generate pwm outputs, and a single,10-bit analog-to-digital converter (adc), which can perform conversion within 1 m s. copyright ? 1999, texas instruments incorporated ti and xds510 are trademarks of texas instruments incorporated. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 2 post office box 1443 ? houston, texas 772511443 table of contents description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device features 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pge package, 144-pin qfp, 'f243 4 . . . . . . . . . . . . . . . . fn package, 68-pin plcc, 'f241 5 . . . . . . . . . . . . . . . . . pg package, 64-pin qfp, 'f241 6 . . . . . . . . . . . . . . . . . . . terminal functions - 'f243 pge package 7 . . . . . . . . . . . terminal functions - 'f241 pg and fn packages 14 . . . functional block diagram 17 . . . . . . . . . . . . . . . . . . . . . . . architectural overview 18 . . . . . . . . . . . . . . . . . . . . . . . . . . system-level functions 18 . . . . . . . . . . . . . . . . . . . . . . . . . device memory maps 18 . . . . . . . . . . . . . . . . . . . . . . . . . . memory maps 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral memory map 21 . . . . . . . . . . . . . . . . . . . . . . . . software-controlled wait-state generator 22 . . . . . . . . digital i/o and shared pin functions 23 . . . . . . . . . . . . . digital i/o control registers 26 . . . . . . . . . . . . . . . . . . . . device reset and interrupts 26 . . . . . . . . . . . . . . . . . . . . clock generation 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block diagram of the '24x dsp cpu 37 . . . . '24x legend for the internal hardware 38 . . . . . . . . . . . 'f243/'f241 dsp core cpu 39 . . . . . . . . . . . . . . . . . . . . . internal memory 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripherals 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external memory interface ('f243 only) 45 . . . . . . . . . . wait-state generation ('f243 only) 46 . . . . . . . . . . . . . . event-manager (ev2) module 47 . . . . . . . . . . . . . . . . . . analog-to-digital converter (adc) module 50 . . . . . . . . a/d overview 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial peripheral interface (spi) module 52 . . . . . . . . . . serial communications interface (sci) module 54 . . . . controller area network (can) module 56 . . . . . . . . . . watchdog (wd) timer module 60 . . . . . . . . . . . . . . . . . . scan-based emulation 62 . . . . . . . . . . . . . . . . . . . . . . . . . . tms320x24x instruction set 62 . . . . . . . . . . . . . . . . . . . . . addressing modes 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . repeat feature 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction set summary 63 . . . . . . . . . . . . . . . . . . . . . . . development support 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . nomenclature 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 72 . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 73 . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 73 . . . . . . . . . . . . . electrical characteristics 73 . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 74 . . . . . . . . . . . . . . signal transition levels 74 . . . . . . . . . . . . . . . . . . . . . . . . timing parameter symbology 75 . . . . . . . . . . . . . . . . . . . general notes on timing parameters 75 . . . . . . . . . . . . clock characteristics and timings 76 . . . . . . . . . . . . . . . . clock options 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ext reference crystal/clock w/pll circuit enabled 77 low-power mode timings 78 . . . . . . . . . . . . . . . . . . . . . . rs timings 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xf, bio , and mp/mc timings 80 . . . . . . . . . . . . . . . . . . . timing event manager interface 81 . . . . . . . . . . . . . . . . . . pwm timings 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture and qep timings 82 . . . . . . . . . . . . . . . . . . . . . . interrupt timings 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output timings 84 . . . . . . . . . . . spi master mode timing parameters 85 . . . . . . . . . . . . . spi slave mode timing parameters 89 . . . . . . . . . . . . . . . external memory interface read timings 93 . . . . . . . . . . external memory interface write timings 95 . . . . . . . . . . external memory interface ready-on-read 97 . . . . . . . . external memory interface ready-on-write 98 . . . . . . . . 10-bit dual analog-to-digital converter (adc) 99 . . . . . . adc operating frequency 99 . . . . . . . . . . . . . . . . . . . . . adc input pin circuit 100 . . . . . . . . . . . . . . . . . . . . . . . . . internal adc module timings 101 . . . . . . . . . . . . . . . . . . flash eeprom 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programming operation 102 . . . . . . . . . . . . . . . . . . . . . . . erase operation 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash-write operation 102 . . . . . . . . . . . . . . . . . . . . . . . . register file compilation 103 . . . . . . . . . . . . . . . . . . . . . . . mechanical data 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 3 post office box 1443 ? houston, texas 772511443 device features table 1 and table 2 provide a comparison of the features of the 'f243 and 'f241. see the functional block diagram for '24x peripherals and memory. table 1. hardware features of the tms320x24x dsp controllers on-chip memory (words) ram external power cycle tms320x24x devices data space configurable data / prog space external memory interfa c e power supply (v) cycle time (ns) (b1 ram - 256 words) (b2 ram - 32 words) (b0 ram) interface tms320f243 288 256 5 50 tms320f241 288 256 5 50 table 2. device specifications of the tms320x24x dsp controllers on-chip memory (words) package tms320x24x devices rom flash eeprom adc channels peripherals gpio package type pin count prog prog can spi pin count tms320f243 8k 8 32 pge 144-pqfp tms320f241 8k 8 26 fn 68-plcc pg 64-pqfp
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 4 post office box 1443 ? houston, texas 772511443 v sso ps v ddo is a0 a1 pwm1/iopa6 a2 pwm2/iopa7 a3 pwm3/iopb0 dnc pwm4/iopb1 a4 pwm5/iopb2 a5 a6 pwm6/iopb3 a7 pdpint a8 tclkin/iopb7 a9 tdir/iopb6 a10 xint1/iopa2 a11 xint2/adcsoc/iopd1 a12 nmi a13 v ccp /wddis a14 v ddo a15 v sso nc nc adcin04 adcin03 nc adcin02 nc adcin01 nc adcin00 nc dnc nc v sso v sso v ss v dd ena_144 rs iopd2 iopd3 tck iopd4 tdi iopd5 tdo iopd6 tms iopd7 trst vis_clk v ss d0 v ddo d1 v sso adcin0 adcin05 144 143 142 141 nc 140 139 nc 138 137 nc 136 135 134 nc 133 132 131 t1pwm/t1cmp/iopb4 130 129 128 127 vis_oe 126 125 124 cap1/qep0/iopa3 123 strb 122 cap2/qep1/iopa4 121 br 120 cap3/iopa5 119 rd 118 117 clkout/iopd0 116 cantx/iopc6 115 r/w 114 canrx/iopc7 113 112 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 d2 xtal1/clkin xtal2 mp/mc ready emu0 d3 emu1/off d4 xf/iopc0 scirxd/iopa1 d9 spisimo/iopc2 d10 spisomi/iopc3 d11 spiclk/iopc4 d12 spiste/iopc5 d13 d14 bio/iopc1 111 v 110 v 109 70 71 72 d15 d7 we d6 d5 d8 pmt dd sso ddo pge package 2 (top view) nc t2pwm/t2cmp/iopb5 scitxd/iopa0 sso v v ss v sso v ds ddo v sso v ss v dd v sso v ddo v adcin06 adcin07 cca v ssa v nc sso v sso v sso v tms320f243 (144-pin qfp) v reflo v refhi 2 nc = no connection, dnc = do not connect
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 5 post office box 1443 ? houston, texas 772511443 v dd 28 29 30 31 32 33 34 tclkin/iopb7 tdir/iopb6 pwm1/iopa6 pdpint 35 36 37 38 39 27 xint1/iopa2 xint2/adcsoc/iopd1 40 41 42 43 8765432168676665 9 64636261 fn package 2 (top view) nmi tck tdi adcin03 rs tdo tms adcin04 trst adcin02 nc 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 15 16 canrx/iopc7 cantx/iopc6 clkout/iopd0 cap3/iopa5 adcin07 v refhi v reflo adcin06 adcin05 60 59 58 57 56 53 52 51 50 49 48 47 46 45 44 55 54 pmt spiste/iopc5 spiclk/iopc4 spisomi/iopc3 spisimo/iopc2 bio /iopc1 v dd v ss xf/iopc0 emu1 emu0 xtal2 v ddo scirxd/iopa1 scitxd/iopa0 v ddo v sso t2cmp/t2pwm/iopb5 t1cmp/t1pwm/iopb4 v ss v cca v ssa v sso v ss v ddo v sso v sso xtal1/clkin v sso v ddo v ccp /wddis cap2/qep1/iopa4 cap1/qep0/iopa3 tms320f241 (68-pin plcc) pwm2/iopa7 pwm3/iopb0 pwm4/iopb1 pwm5/iopb2 pwm6/iopb3 adcin01 adcin00 dnc 2 nc = no connection, dnc = do not connect
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 6 post office box 1443 ? houston, texas 772511443 v ccp /wddis nmi xint2/adcsoc/iopd1 xint1/iopa2 tdir/iopb6 tclkin/iopb7 pdpint pwm6/iopb3 pwm5/iopb2 pwm4/iopb1 pwm3/iopb0 pwm2/iopa7 pwm1/iopa6 trst tms tdo tdi tck rs v sso dnc adcin00 adcin01 adcin02 adcin03 adcin04 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 pmt spiste/iopc5 spiclk/iopc4 spisomi/iopc3 spisimo/iopc2 scirxd/iopa1 scitxd/iopa0 bio/iopc1 xf/iopc0 emu1 emu0 xtal2 xtal1/clkin canrx/iopc7 cantx/iopc6 clkout/iopd0 cap3/iopa5 cap2/qep1/iopa4 cap1/qep0/iopa3 t2cmp/t2pwm/iopb5 t1cmp/t1pwm/iopb4 adcin07 adcin06 pg package 2 (top view) tms320f241 (64-pin qfp) v sso v ddo v ss v dd v sso v ddo 2 nc = no connection, dnc = do not connect v dd v ss v ssa v cca v ddo v sso v refhi adcin05 v reflo
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 7 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package name 144 qfp type 2 reset state 3 description no. state 3 analog-to-digital converter (adc) inputs adcin00 10 adcin01 8 adcin02 6 adcin03 4 i i analog in p uts to the adc adcin04 3 i i analog inp u ts to the adc adcin05 144 adcin06 143 adcin07 139 v cca 137 analog supply voltage for adc (5 v). v cca must be isolated from digital supply voltage. v ssa 135 analog ground reference for adc v refhi 141 adc analog high-voltage reference input v reflo 142 adc analog low-voltage reference input event manager t1pwm/t1cmp/ iopb4 130 i/o/z i timer 1 compare output/general-purpose bidirectional digital i/o (gpio). t2pwm/t2cmp/ iopb5 128 i/o/z i timer 2 compare output/gpio tdir/ iopb6 85 i/o i counting direction for general-purpose (gp) timer/gpio. if tdir=1, upward counting is selected. if tdir=0, downward counting is selected. tclkin/ iopb7 87 i/o i external clock input for gp timer/gpio. note that timer can also use the internal device clock. cap1/qep0/ iopa3 123 i/o i capture input #1/quadrature encoder pulse input #0/gpio cap2/qep1/ iopa4 121 i/o i capture input #2/quadrature encoder pulse input #1/gpio cap3/ iopa5 119 i/o i capture input #3/gpio pwm1/ iopa6 102 i/o/z i compare/pwm output pin #1 or gpio pwm2/ iopa7 100 i/o/z i compare/pwm output pin #2 or gpio pwm3/ iopb0 98 i/o/z i compare/pwm output pin #3 or gpio pwm4/ iopb1 96 i/o/z i compare/pwm output pin #4 or gpio pwm5/ iopb2 94 i/o/z i compare/pwm output pin #5 or gpio pwm6/ iopb3 91 i/o/z i compare/pwm output pin #6 or gpio pdpint 89 i i power drive protection interrupt input. this interrupt, when activated, puts the pwm output pins in the high-impedance state should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. pdpint is a falling-edge-sensitive interrupt. after the falling edge, this pin must be held low for two clock cycles for the core to recognize the interrupt. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 8 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 serial peripheral interface (spi) and bit i/o pins spisimo/ iopc2 60 i/o i spi slave in, master out or gpio spisomi/ iopc3 62 i/o i spi slave out, master in or gpio spiclk/ iopc4 64 i/o i spi clock or gpio spiste/ iopc5 66 i/o i spi slave transmit enable (optional) or gpio serial communications interface (sci) and bit i/o pins scitxd/ iopa0 56 i/o i sci asynchronous serial port transmit data or gpio scirxd/ iopa1 58 i/o i sci asynchronous serial port receive data or gpio controller area network (can) cantx/ iopc6 115 i/o i can transmit data or gpio canrx/ iopc7 113 i/o i can receive data or gpio interrupt, external access, and miscellaneous signals rs 19 i/o i device reset. rs causes the 'f243/241 to terminate execution and sets pc = 0. when rs is brought to a high level, execution begins at location zero of program memory. rs affects (or sets to zero) various registers and status bits. when the watchdog timer overflows, it initiates a system reset pulse that is reflected on the rs pin. this pulse is eight clock cycles wide. nmi 79 i i nonmaskable interrupt. when nmi is activated, the device is interrupted regardless of the state of the intm bit of the status register. nmi is (falling) edge- and low-level-sensitive. to be recognized by the core, this pin must be kept low for at least one clock cycle after the falling edge. xint1/ iopa2 83 i/o i external user interrupt 1 or gpio. both xint1 and xint2 are edge- sensitive. to be recognized by the core, these pins must be kept high/low for at least one clock cycle after the edge. the edge polarity is programmable. xint2/adcsoc/ iopd1 81 i/o i external user interrupt 2. external astart-of-conversiono input for adc/gpio. both xint1 and xint2 are edge-sensitive. to be recognized by the core, these pins must be kept high/low for at least one clock cycle after the edge. the edge polarity is programmable. mp/mc 43 i i microprocessor/microcomputer mode select. if this pin is low during reset, the device is put in microcomputer mode and program execution begins at 0000h of internal program memory (flash eeprom). a high value during reset puts the device in microprocessor mode and program execution begins at 0000h of external program memory. ready 44 i i ready is pulled low to add wait states for external accesses. ready indicates that an external device is prepared for a bus transaction to be completed. if the device is not ready, it pulls the ready pin low. the processor waits one cycle and checks ready again. note that the processor performs ready-detection if at least one software wait state is programmed. to meet the external ready timings, the wait-state generator control register (wsgr) should be programmed for at least one wait state. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 9 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 interrupt, external access, and miscellaneous signals (continued) is 105 i/o, data, and program space strobe select signals. is, ds, and ps are always high l l l l t d f t th l t t l i/o is ds ps 105 110 o/z 1 unless low-level asserted for access to the relevant external memory space or i/o. they are p laced in the high - im p edance state during reset, p ower down, and when ps 107 they are laced in the high-im edance state during reset , ower down , and when emu1/off is active low. we 112 o/z 1 write enable strobe. the falling edge of we indicates that the device is driving the external data bus (d15 d0). we is active on all external program, data, and i/o writes. we goes in the high-impedance state when emu1/off is active low. rd 118 o 1 read enable strobe. read-select indicates an active, external read cycle. rd is active on all external program, data, and i / o reads. rd goes into the high-impedance state when emu1/off is active low. r/w 114 o/z 1 read/write signal. r/w indicates transfer direction during communication to an external device. it is normally in read mode (high), unless low level is asserted for performing a write operation. it is placed in the high-impedance state when emu1/off is active low and during power down. strb 122 o/z 1 external memory access strobe. strb is always high unless asserted low to indicate an external bus cycle. strb is active for all off-chip accesses. it is placed in the high-impedance state during power down, and when emu1/off is active low. br 120 o/z 1 bus request, global memory strobe. br is asserted during access of external global data memory space. br can be used to extend the data memory address space by up to 32k words. br goes in the high-impedance state during reset, power down, and when emu1/off is active low. vis_clk 31 o 0 visibility clock. same as clkout, but timing is aligned for external buses in visibility mode. ena_144 18 i i active high to enable external interface signals. if pulled low, the 'f243 behaves like an 'f241ei.e., it has no external memory and generates an illegal address if any of the three external spaces are accessed (is , ds , ps asserted). this pin has an internal pulldown. vis_oe 126 o 0 this pin is active (low) whenever the external databus is driving as an output during visibility mode. can be used by external decode logic to prevent data bus contention while running in visibility mode. xf /iopc0 49 i/o o 1 external flag output (latched software-programmable signal). xf is a general-purpose output pin. it is set/reset by the setc xf/clrc xf instruction. this pin is configured as an external flag output by all device resets. it can be used as a gpio, if not used as xf. bio /iopc1 55 i/o i branch control input. bio is polled by the bcnd pma,bio instruction. if bio is low, a branch is executed. if bio is not used, it should be pulled high. this pin is configured as a branch control input by all device resets. it can be used as a gpio, if not used as a branch control input. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 10 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 interrupt, external access, and miscellaneous signals (continued) pmt 68 i i enables parallel module test (pmt). do not connect, reserved for test. v ccp /wddis 77 i i flash programming voltage pin and watchdog disable. this is the 5-v supply used for flash programming. flash cannot be programmed if this pin is held at 0 v. this pin also works as a hardware watchdog disable, when v ccp /wddis = +5 v and bit 6 in wdcr is set to 1. dedicated i/o signals iopd2 20 i/o dedicated gpio port d bit 2 iopd3 21 i/o dedicated gpio port d bit 3 iopd4 23 i/o i dedicated gpio port d bit 4 iopd5 25 i/o i dedicated gpio port d bit 5 iopd6 27 i/o dedicated gpio port d bit 6 iopd7 29 i/o dedicated gpio port d bit 7 data and address bus signals d0 33 ? d1 35 ? d2 38 ? d3 46 ? d4 48 ? d5 50 ? d6 52 ? d7 54 i/o/z o ? bit x of the 16 bit data bus d8 57 i/o/z o ? bit x of the 16 - bit data b u s d9 59 d10 61 d11 63 d12 65 d13 67 d14 69 d15 71 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 11 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 data and address bus signals (continued) a0 104 a1 103 a2 101 a3 99 a4 95 a5 93 a6 92 a7 90 o 0 bit x of the 16 bit address bus a8 88 o 0 bit x of the 16 - bit address b u s a9 86 a10 84 a11 82 a12 80 a13 78 a14 76 a15 74 clock signals xtal1/clkin 41 i i pll oscillator input pin. crystal input to pll/clock source input to pll. xtal1/clkin is tied to one side of a reference crystal. xtal2 42 o o crystal output. pll oscillator output pin. xtal2 is tied to one side of a reference crystal. this pin goes in the high-impedance state when emu1/off is active low. clkout /iopd0 116 i/o o clock output. this pin outputs either the cpu clock (clkout) or the watchdog clock (wdclk). the selection is made by the clksrc bit (bit 14) of the system control and status register (scsr). this pin can be used as a gpio if not used as a clock output pin. test signals tck 22 i i jtag test clock with internal pullup tdi 24 i i jtag test data input (tdi) with internal pullup. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. tdo 26 i/o i jtag scan out, test data output (tdo). the contents of the selected register (instruction or data) is shifted out of tdo on the falling edge of tck. tms 28 i i jtag test-mode select (tms) with internal pullup. this serial control input is clocked into the tap controller on the rising edge of tck. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 12 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 test signals (continued) trst 30 i i jtag test reset with internal pulldown. trst , when driven high, gives the scan system control of the operations of the device. if this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. emu0 45 i/o i emulator i/o pin 0 with internal pullup. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the jtag scan. emu1/off 47 i/o i emulator i/o pin 1 with internal pullup. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through jtag scan. supply signals 14 15 36 36 37 40 70 70 v sso 73 digital logic and buffer ground reference 108 111 117 124 129 129 131 34 39 v ddo 72 digital logic and buffer su pp ly voltage v ddo 75 digital logic and b u ffer s u ppl y v oltage 106 109 17 v dd 53 digital logic supply voltage 125 16 v ss 32 digital logic ground reference v ss 51 digital logic gro u nd reference 127 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 13 post office box 1443 ? houston, texas 772511443 terminal functions - 'f243 pge package (continued) name 144 qfp type 2 reset state 3 description no. state 3 no connects dnc 12 do not connect reserved for test dnc 97 do not connect . reser v ed for test . 1 2 5 7 9 11 nc 13 no internal connection made to this p in nc 13 no internal connection made to this pin 132 133 134 136 138 140 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. ? data is in output mode when avis is enabled. at reset, the device comes up with avis mode enabled. the data bus is in output mo de while avis is enabled. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 14 post office box 1443 ? houston, texas 772511443 terminal functions - 'f241 pg and fn packages name 64 qfp 68 plcc type 2 reset state 3 description no. no. state 3 interface control signals v ccp /wddis 52 63 i i flash programming voltage supply pin. this is the 5-v supply used for flash programming. flash cannot be programmed if this pin is held at 0 v. this pin also works as a hardware watchdog disable, when v ccp /wddis = +5 v and bit 6 in wdcr is set to 1. note that on rom devices, only the wddis function is valid. analog-to-digital converter (adc) inputs adcin00 24 32 adcin01 23 31 adcin02 22 30 adcin03 21 29 i i analog in p uts to the adc adcin04 20 28 i i analog inp u ts to the adc adcin05 19 26 adcin06 18 25 adcin07 15 22 v cca 14 21 analog supply voltage for adc (5 v). v cca must be isolated from digital supply voltage. v ssa 13 20 analog ground reference for adc v refhi 16 23 adc analog high-voltage reference input v reflo 17 24 adc analog low-voltage reference input event manager t1cmp/t1pwm/ iopb4 12 19 i/o/z timer 1 compare output/general-purpose bidirectional digital i/o (gpio). t2cmp/t2pwm/ iopb5 11 18 i/o/z timer 2 compare output/gpio tdir/ iopb6 56 67 i/o counting direction for gp timer/gpio. if tdir=1, upward counting is selected. if tdir=0, downward counting is selected. tclkin/ iopb7 57 68 i/o external clock input for gp timer/gpio. note that timer can also use the internal device clock. cap1/qep0/ iopa3 8 15 i/o capture input #1/quadrature encoder pulse input #0/gpio cap2/qep1/ iopa4 7 14 i/o i capture input #2/quadrature encoder pulse input #1/gpio cap3/ iopa5 6 13 i/o i capture input #3/gpio pwm1/ iopa6 64 7 i/o/z compare/pwm output pin #1 or gpio pwm2/ iopa7 63 6 i/o/z compare/pwm output pin #2 or gpio pwm3/ iopb0 62 5 i/o/z compare/pwm output pin #3 or gpio pwm4/ iopb1 61 4 i/o/z compare/pwm output pin #4 or gpio pwm5/ iopb2 60 3 i/o/z compare/pwm output pin #5 or gpio pwm6/ iopb3 59 2 i/o/z compare/pwm output pin #6 or gpio pdpint 58 1 i i power drive protection interrupt input. this interrupt, when activated, puts the pwm output pins in the high-impedance state, should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. pdpint is a falling-edge-sensitive interrupt. after the falling edge, this pin must be held low for two clock cycles for the core to recognize the interrupt. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 15 post office box 1443 ? houston, texas 772511443 terminal functions - 'f241 pg and fn packages (continued) name 64 qfp 68 plcc type 2 reset state 3 description no. no. state 3 serial peripheral interface (spi) and bit i/o pins spisimo/ iopc2 45 56 i/o spi slave in, master out or gpio spisomi/ iopc3 46 57 i/o i spi slave out, master in or gpio spiclk/ iopc4 47 58 i/o i spi clock or gpio spiste/ iopc5 48 59 i/o spi slave transmit enable (optional) or gpio serial communications interface (sci) and bit i/o pins scitxd/ iopa0 43 54 i/o i sci asynchronous serial port transmit data or gpio scirxd/ iopa1 44 55 i/o i sci asynchronous serial port receive data or gpio controller area network (can) cantx/ iopc6 4 11 i/o i can transmit data or gpio canrx/ iopc7 3 10 i/o i can receive data or gpio interrupt, external access, and miscellaneous signals rs 27 35 i/o i device reset. rs causes the 'f243/241 to terminate execution and sets pc = 0. when rs is brought to a high level, execution begins at location zero of program memory. rs affects (or sets to zero) various registers and status bits. when the watchdog timer overflows, it initiates a system reset pulse that is reflected on the rs pin. this pulse is eight clock cycles wide. nmi 53 64 i i nonmaskable interrupt. when nmi is activated, the device is interrupted regardless of the state of the intm bit of the status register. nmi is (falling) edge- and low-level-sensitive. to be recognized by the core, this pin must be kept low for at least one clock cycle after the falling edge. xint1/ iopa2 55 66 i/o i external user interrupt 1 or gpio. both xint1 and xint2 are edge- sensitive. to be recognized by the core, these pins must be kept low/high for at least one clock cycle after the edge. the edge polarity is programmable. xint2/adcsoc/ iopd1 54 65 i/o i external user interrupt 2. external astart-of-conversiono input for adc/gpio. both xint1 and xint2 are edge-sensitive. to be recognized by the core, these pins must be kept low/high for at least one clock cycle after the edge. the edge polarity is programmable. xf /iopc0 39 50 i/o o 1 external flag output (latched software-programmable signal). xf is a general-purpose output pin. it is set/reset by the setc xf/clrc xf instruction. this pin is configured as an external flag output by all device resets. it can be used as a gpio, if not used as xf. bio /iopc1 42 53 i/o i branch control input. bio is polled by the bcnd pma,bio instruction. if bio is low, a branch is executed. if bio is not used, it should be pulled high. this pin is configured as a branch control input by all device resets. it can be used as a gpio, if not used as a branch control input. pmt 49 60 i i enables parallel module test (pmt). do not connect, reserved for test. clock signals xtal1/clkin 35 46 i i pll oscillator input pin. crystal input to pll/clock source input to pll. xtal1/clkin is tied to one side of a reference crystal. xtal2 36 47 o o crystal output. pll oscillator output pin. xtal2 is tied to one side of a reference crystal. this pin goes in the high-impedance state when emu1/off is active low. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 16 post office box 1443 ? houston, texas 772511443 terminal functions - 'f241 pg and fn packages (continued) name 64 qfp 68 plcc type 2 reset state 3 description no. no. state 3 clock signals (continued) clkout /iopd0 5 12 i/o o clock output. this pin outputs either the cpu clock (clkout) or the watchdog clock (wdclk). the selection is made by the clksrc bit (bit 14) of the system status and control register (sscr). this pin can be used as a gpio if not used as a clock output pin. test signals tck 28 36 i i jtag test clock with internal pullup tdi 29 37 i i jtag test data input (tdi) with internal pullup. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. tdo 30 38 o i jtag scan out, test data output (tdo). the contents of the selected register (instruction or data) is shifted out of tdo on the falling edge of tck. tms 31 39 i i jtag test-mode select (tms) with internal pullup. this serial control input is clocked into the tap controller on the rising edge of tck. trst 32 40 i i jtag test reset with internal pulldown. trst , when driven high, gives the scan system control of the operations of the device. if this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. emu0 37 48 i/o i emulator i/o pin 0 with internal pullup. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the jtag scan. emu1 38 49 i/o i emulator i/o pin 1 with internal pullup. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through jtag scan. supply signals v dd 9 16 digital logic su pp ly voltage (5 v) v dd 41 52 digital logic s u ppl y v oltage (5 v) 42 v ddo 1 8 digital logic and buffer su pp ly voltage (5 v) v ddo 34 45 digital logic and b u ffer s u ppl y v oltage (5 v) 51 62 41 v ss 10 17 digital logic ground reference 40 51 43 2 9 v sso 26 34 digital logic and buffer ground reference 33 44 50 61 no connect nc 27 no internal connection made to this pin dnc 25 33 do not connect. reserved for test. 2 i = input, o = output, z = high impedance 3 the reset state indicates the state of the pin at reset. if the pin is an input, indicated by an i, its state is determined by user design. if the pin is an output, its level at reset is indicated. in silicon revisions 2.0-tmx and 2.1-tms, this pin is level-sensitive and can cause multiple interrupts when held low. note: bold, italicized pin names indicate pin function after reset.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 17 post office box 1443 ? houston, texas 772511443 functional block diagram of the '24x dsp controller 2 4 8 pdpint 3 2 8 7 quadrature encoder pulse (qep) capture/ units compare timers purpose general- manager event emulation test/ peripheral bus timer watchdog interface communications serial- interface peripheral serial- converter to-digital analog- single 10-bit data bus 2 module clock program bus b1/b2 daram b0 daram flash eeprom initialization interrupts control memory 2 controller program cpu 'c2xx shifter product preg treg multiplier shifter output accumulator alu shifter input registers mapped memory registers auxiliary registers control status/ arau register instruction 32 3 4 interrupts resets general- purpose i/o pins 2 can module 16 16 2 'f243 only 3 26 in 'f241
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 18 post office box 1443 ? houston, texas 772511443 architectural overview the functional block diagram provides a high-level description of each component in the 'f243/'f241 dsp controllers. the tms320x24x devices are composed of three main functional units: a 'c2xx dsp core, internal memory, and peripherals. in addition to these three functional units, there are several system-level features of the 'f243/'f241 that are distributed. these system features include the memory map, device reset, interrupts, digital input / output (i / o), clock generation, and low-power operation. system-level functions device memory maps the 'f243/'f241 devices implement three separate address spaces for program memory, data memory, and i/o space. on the 'f243/'f241, the first 96 (05fh) data memory locations are either allocated for memory-mapped registers or reserved. this memory-mapped register space contains various control and status registers, including those for the cpu. all the on-chip peripherals of the 'f243/'f241 devices are mapped into data memory space. access to these registers is made by the cpu instructions addressing their data memory locations. figure 1 shows the 'f243 memory map and figure 2 shows the 'f241 memory map.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 19 post office box 1443 ? houston, texas 772511443 memory maps aaaaaaa aaaaaaa aaaaaaa aaaaaaa reserved/ illegal aaaaaaa aaaaaaa aaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa reserved/ illegal reserved/ illegal aaaaaa aaaaaa aaaaaa 0000 005f 0060 01ff 02ff 0300 0200 03ff 0400 7000 peripheral memory- mapped registers (system,wd, adc, sci, spi, can, i/o, interrupts) 73ff 7400 743f 7440 data hex 007f 0080 8000 external ffff 7fff memory-mapped registers/reserved addresses on-chip daram b2 on-chip daram (b0) 3 (cnf = 0) reserved (cnf = 1) on-chip daram (b1) 6fff peripheral memory-mapped registers (event manager) 0000 002f 0030 feff fdff fe00 hex 1fff 2000 external on-chip daram (b0) 2 (cnf = 1) external (cnf = 0) program ff00 ffff illegal interrupts reserved 2 (cnf = 1) external (cnf = 0) unused 0000 external ff0e i/o hex ffff wait-state generator control register (on-chip) flash control mode register reserved feff ff00 ff10 fffe ff0f on-chip flash memory, (8k) if mp/mc = 0 external program memory if mp/mc = 1 2 when cnf = 1, addresses fe00hfeffh and ff00hffffh are mapped to the same physical block (b0) in program-memory space. for example, a write to fe00h will have the same effect as a write to ff00h. for simplicity, addresses fe00hfeffh are referred to as reserved when cnf = 1. 3 when cnf = 0, addresses 0100h01ffh and 0200h02ffh are mapped to the same physical block (b0) in data-memory space. for exampl e, a write to 0100h will have the same effect as a write to 0200h. for simplicity, addresses 0100h01ffh are referred to as reserv ed. addresses 0300h03ffh and 0400h04ffh are mapped to the same physical block (b1) in data-memory space. for example, a write to 0400h has the same effect as a write to 0300h. for simplicity, addresses 0400h04ffh are referred to as reserved. figure 1. tms320f243 memory map
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 20 post office box 1443 ? houston, texas 772511443 memory maps (continued) aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa reserved reserved unused reserved/ illegal reserved/ illegal 0000 interrupts 002f 0030 hex program 1fff 2000 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 0000 005f 0060 01ff 02ff 0300 0200 03ff 0400 7000 peripheral memory- mapped registers (system,wd, adc, sci, spi, can, i/o, interrupts) 73ff 7400 743f 7440 data hex 007f 0080 8000 reserved ffff 7fff memory-mapped registers/reserved addresses on-chip daram b2 on-chip daram (b0) 3 (cnf = 0) reserved (cnf = 1) on-chip daram (b1) 6fff peripheral memory-mapped registers (event manager) illegal fdff fe00 on-chip daram b0 2 (cnf = 1) external (cnf = 0) reserved 2 (cnf = 1) external (cnf = 0) feff ff00 reserved ffff on-chip flash memory, (8k) if mp/mc = 0 external program memory if mp/mc = 1 0000 ff0e i/o hex ffff flash control mode register ff10 ff0f 2 when cnf = 1, addresses fe00hfeffh and ff00hffffh are mapped to the same physical block (b0) in program-memory space. for example, a write to fe00h will have the same effect as a write to ff00h. for simplicity, addresses fe00hfeffh are referred to as reserved when cnf = 1. 3 when cnf = 0, addresses 0100h01ffh and 0200h02ffh are mapped to the same physical block (b0) in data-memory space. for exampl e, a write to 0100h will have the same effect as a write to 0200h. for simplicity, addresses 0100h01ffh are referred to as reserv ed. addresses 0300h03ffh and 0400h04ffh are mapped to the same physical block (b1) in data-memory space. for example, a write to 0400h has the same effect as a write to 0300h. for simplicity, addresses 0400h04ffh are referred to as reserved. note a: there is no external memory space for program, data, or i/o in the 'f241. figure 2. tms320f241 memory map
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 21 post office box 1443 ? houston, texas 772511443 peripheral memory map the system and peripheral control register frame contains all the data, status, and control bits to operate the system and peripheral modules on the device (excluding the event manager). the register frame is mapped in the data memory space. illegal global-memory allocation register 0000 0003 0004 0005 0000 memory-mapped registers and reserved 005f 0060 on-chip daram b2 02ff 0300 01ff 0200 03ff on-chip daram b1 0400 reserved 73ff peripheral frame 1 (pf1) 7400 77ff 7800 external 2 ffff 7000 700f reserved 0007 emulation registers and reserved peripheral frame 2 (pf2) reserved on-chip daram b0 interrupt-mask register illegal system configuration and control registers watchdog timer registers illegal digital-i/o control registers illegal reserved interrupt mask, vector and flag registers 0006 005f 007f 0080 07ff 7000 743f 7440 7010 701f 7020 702f 7030 703f 7040 704f 7050 705f 7060 706f 7070 707f 7080 708f 7090 709f 70a070ff 7400 7408 7411 7419 7420 7429 742c 7431 7432 743f interrupt flag register spi sci illegal external-interrupt registers adc control registers general-purpose timer registers capture & qep registers compare, pwm, and deadband registers reserved 7fff 8000 illegal 0800 6fff illegal hex hex can control registers 7100722f 723073ff 2 reserved in the 'f241 figure 3. peripheral memory map for 'f243/'f241
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 22 post office box 1443 ? houston, texas 772511443 software-controlled wait-state generator due to the fast cycle time of the 'f243 devices, it is often necessary to operate with wait states to interface with external logic or memory. for many systems, one wait state is adequate. the software wait-state generator can be programmed to generate between 0 and 7 wait states for a given space. software wait states are configured through the wait-state generator register (wsgr). the wsgr includes three 3-bit fields to configure wait states for the following external memory spaces: data space (dsws), program space (psws), and i/o space (isws). the wait-state generator enables wait states for a given memory space based on the value of the corresponding three bits, regardless of the condition of the ready signal. the ready signal can be used to generate additional wait states. all bits of the wsgr are set to 1 at reset so that the device can operate from slow memory at reset. the wsgr register (shown in table 3, table 4 and table 5) resides at i / o location ffffh. this register should not be accessed in the 'f241. table 3. wait-state generator control register ( wsgr) 15 12 11 10 9 8 6 5 3 2 0 reserved bvis isws dsws psws 0 r/w11 r/w111 r/w111 r/w111 legend: 0 = always read as zeros, r = read access, w= write access, n = value after reset table 4. wait-state(s) programming psws, dsws, isws bits wait states for program, data, or i / o 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 table 5. wait-state generator control register ( wsgr) bits name description 20 psws external program space wait states. psws determines that between 0 to 7 wait states are applied to all reads and writes to off-chip program space address. the memory cycle can be further extended by using the ready signal. the ready signal does not override the wait states generated by psws. these bits are set to 1 (active) by reset (rs ). 53 dsws external data space wait states. dsws determines that between 0 to 7 wait states are applied to all reads and writes to off-chip data space. the memory cycle can be further extended by using the ready signal. the ready signal does not override the wait states generated by dsws. these bits are set to 1 (active) by reset (rs ). 86 isws external input / output space wait state. isws determines that between 0 to 7 wait states are applied to all reads and writes to off-chip i / o space. the memory cycle can be further extended by using the ready signal. the ready signal does not override the wait states generated by isws. these bits are set to 1 (active) by reset (rs ). 10 9 bvis bus visibility modes. bits 10 and 9 allow selection of various bus visibility modes while running from internal program and/or data memory. these modes provide a method of tracing internal bus activity. these bits are set to 11b by reset (rs ), causing internal program address and program data to be output on the external address and data pins. see table 6. 15 11 reserved
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 23 post office box 1443 ? houston, texas 772511443 software-controlled wait-state generator (continued) table 6. visibility modes bit 10 bit 9 visibility mode 0 0 bus visibility off (reduces power consumption and noise) 0 1 bus visibility off (reduces power consumption and noise) 1 0 data-address bus output to external address bus. data-data bus output to external data bus. 1 1 program-address bus output to external address bus. program-data bus output to external data bus. digital i/o and shared pin functions the 'f243 has a total of 32 general-purpose, bidirectional, digital i/o (gpio) pins that function as follows: six pins are dedicated i/o pins (see table 7) and 26 pins are shared between primary functions and i/o. the 'f241 has 26 i/o pins; all are shared with other functions. the digital i/o ports module provides a flexible method for controlling both dedicated i/o and shared pin functions. all i/o and shared pin functions are controlled using eight 16-bit registers. these registers are divided into two types: output control registers e used to control the multiplexer selection that chooses between the primary function of a pin or the general-purpose i/o function. data and control registers e used to control the data and data direction of bidirectional i/o pins. table 7. dedicated i/o pins ('f243 only) 'f243 pin number pin name 20 iopd2 21 iopd3 23 iopd4 25 iopd5 27 iopd6 29 iopd7 description of shared i/o pins the control structure for shared i/o pins is shown in figure 4, where each pin has three bits that define its operation: mux control bit e this bit selects between the primary function (1) and i/o function (0) of the pin. i/o direction bit e if the i/o function is selected for the pin (mux control bit is set to 0), this bit determines whether the pin is an input (0) or an output (1). i/o data bit e if the i/o function is selected for the pin (mux control bit is set to 0) and the direction selected is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. the mux control bit, i/o direction bit, and i/o data bit are in the i/o control registers.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 24 post office box 1443 ? houston, texas 772511443 description of shared i/o pins (continued) primary function pin (read/write) iop data bit in out 0 = input 1 = output 01 mux control bit 0 = i/o function 1 = primary function iop dir bit primary function or i/o pin when the mux control bit = 1, the primary function is selected in all cases except for the following pins: 1. xf/iopc0 (0 = primary function) 2. bio /iopc1 (0 = primary function) 3. clkout/iopd0 (0 = primary function) note: figure 4. shared pin configuration a summary of shared pin configurations and associated bits is shown in table 8.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 25 post office box 1443 ? houston, texas 772511443 description of shared i/o pins (continued) table 8. shared pin configurations pin # mux control pin function selected i/o port data and direction 2 144 pqfp 68 plcc 64 qfp register (name.bit #) (ocrx.n = 1) (ocrx.n = 0) register data bit # 3 dir bit # 'f243 'f241 56 54 43 ocra.0 scitxd iopa0 padatdir 0 8 58 55 44 ocra.1 scirxd iopa1 padatdir 1 9 83 66 55 ocra.2 xint1 iopa2 padatdir 2 10 123 15 8 ocra.3 cap1/qep0 iopa3 padatdir 3 11 121 14 7 ocra.4 cap2/qep1 iopa4 padatdir 4 12 119 13 6 ocra.5 cap3 iopa5 padatdir 5 13 102 7 64 ocra.6 pwm1 iopa6 padatdir 6 14 100 6 63 ocra.7 pwm2 iopa7 padatdir 7 15 98 5 62 ocra.8 pwm3 iopb0 pbdatdir 0 8 96 4 61 ocra.9 pwm4 iopb1 pbdatdir 1 9 94 3 60 ocra.10 pwm5 iopb2 pbdatdir 2 10 91 2 59 ocra.11 pwm6 iopb3 pbdatdir 3 11 130 19 12 ocra.12 t1pwm/t1cmp iopb4 pbdatdir 4 12 128 18 11 ocra.13 t2pwm/t2cmp iopb5 pbdatdir 5 13 85 67 56 ocra.14 tdir iopb6 pbdatdir 6 14 87 68 57 ocra.15 tclkin iopb7 pbdatdir 7 15 49 50 39 ocrb.0 iopc0 xf pcdatdir 0 8 55 53 42 ocrb.1 iopc1 bio pcdatdir 1 9 60 56 45 ocrb.2 spisimo iopc2 pcdatdir 2 10 62 57 46 ocrb.3 spisomi iopc3 pcdatdir 3 11 64 58 47 ocrb.4 spiclk iopc4 pcdatdir 4 12 66 59 48 ocrb.5 spiste iopc5 pcdatdir 5 13 115 11 4 ocrb.6 cantx iopc6 pcdatdir 6 14 113 10 3 ocrb.7 canrx iopc7 pcdatdir 7 15 116 12 5 ocrb.8 iopd0 clkout pddatdir 0 8 81 65 54 ocrb.9 xint2/adcsoc iopd1 pddatdir 1 9 2 valid only if the i/o function is selected on the pin. 3 if the gpio pin is configured as an output, these bits can be written to. if the pin is configured as an input, these bits are read from. if the dir bit is 0, the gpio pin functions as an input. for a value of 1, the pin is configured as an output. note: gpio pins iopd2 to iopd7 are dedicated i/o pins in 'f243. these pins are not available in the 'f241.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 26 post office box 1443 ? houston, texas 772511443 digital i/o control registers table 9 lists the registers available in the digital i/o module. as with other 'f243/'f241 peripherals, the registers are memory-mapped to the data space. table 9. addresses of digital i/o control registers address register name 7090h ocra i/o mux control register a 7092h ocrb i/o mux control register b 7098h padatdir i/o port a data and direction register 709ah pbdatdir i/o port b data and direction register 709ch pcdatdir i/o port c data and direction register 709eh pddatdir i/o port d data and direction register device reset and interrupts the tms320x24x software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. the 'f243/'f241 recognizes three types of interrupt sources: reset (hardware- or software-initiated) is unarbitrated by the cpu and takes immediate priority over any other executing functions. all maskable interrupts are disabled until the reset service routine enables them. the 'f243/'f241 devices have two sources of reset: an external reset pin and a watchdog timer timeout (reset). hardware-generated interrupts are requested by external pins or by on-chip peripherals. there are two types: external interrupts are generated by one of four external pins corresponding to the interrupts xint1, xint2, pdpint , and nmi . the first three can be masked both by dedicated enable bits and by the cpu's interrupt mask register (imr), which can mask each maskable interrupt line at the dsp core. nmi , which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. it can be locked out only by an already executing nmi or a reset. peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager, spi, sci, wd, can, and adc. they can be masked both by enable bits for each e vent in each peripheral and by the cpu's imr, which can mask each maskable interrupt line at the dsp core. software-generated interrupts for the 'f243/'f241 devices include: the intr instruction. this instruction allows initialization of any 'f243/'f241 interrupt with software. its operand indicates the interrupt vector location to which the cpu branches. this instruction globally disables maskable interrupts (sets the intm bit to 1). the nmi instruction. this instruction forces a branch to interrupt vector location 24h, the same location used for the nonmaskable hardware interrupt nmi. nmi can be initiated by driving the nmi pin low or by executing an nmi instruction. this instruction globally disables maskable interrupts. the trap instruction. this instruction forces the cpu to branch to interrupt vector location 22h. the trap instruction does not disable maskable interrupts (intm is not set to 1); therefore, when the cpu branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. an emulator trap. this interrupt can be generated with either an intr instruction or a trap instruction.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 27 post office box 1443 ? houston, texas 772511443 reset the reset operation ensures an orderly startup sequence for the device. there are two possible causes of a reset, as shown in figure 5. signal reset system reset watchdog timer reset external reset (rs ) pin active figure 5. reset signals the two possible reset signals are generated as follows: watchdog timer reset. a watchdog-timer-generated reset occurs if the watchdog timer overflows or an improper value is written to either the watchdog key register or the watchdog control register. (note that when the device is powered on, the watchdog timer is automatically active.) the watchdog timer reset is reflected on the external rs pin also. reset pin active. to generate an external reset pulse on the rs pin, a low-level pulse duration of at least one cpuclk cycle is necessary to ensure that the device recognizes the reset signal. once watchdog reset is activated, the external rs pin is driven (active) low for a minimum of eight cpuclk cycles. this allows the tms320x24x device to reset external system components. the occurrence of a reset condition causes the tms320x24x to terminate program execution and affects various registers and status bits. during a reset, ram contents remain unchanged, and all control bits that are affected by a reset are initialized to their reset state. hardware-generated interrupts the '24x cpu supports one nonmaskable interrupt (nmi) and six maskable prioritized interrupt requests. the '24x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in response to many events. the '24x cpu does not have sufficient interrupt requests to handle all these peripheral interrupt requests; therefore, a centralized interrupt controller is provided to arbitrate the interrupt requests from all the different sources. throughout this section, refer to figure 6 .
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 28 post office box 1443 ? houston, texas 772511443 hardware-generated interrupts (continued) cpu iack bus addr bus data pivr & logic pirqr# piack# irq gen level 6 irq gen level 5 irq gen level 4 irq gen level 3 irq gen level 2 irq gen level 1 xint2 xint1 adcint canerint canmbint txint rxint spiint capint3 capint2 capint1 tofint2 tufint2 tcint2 tpint2 tofint1 tufint1 tcint1 tpint1 cmp3int cmp2int cmp1int canerint canmbint txint rxint spiint xint2 xint1 adcint pdpint int1 int2 int3 int4 int6 int5 imr ifr irq pulse gen unit figure 6. peripheral interrupt expansion block diagram interrupt hierarchy the number of interrupt requests available is expanded by having two levels of hierarchy in the interrupt request system. there are two levels of hierarchy in both the interrupt request/acknowledge hardware and in the interrupt service routine software.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 29 post office box 1443 ? houston, texas 772511443 interrupt request structure 1. at the lower level of the hierarchy, the peripheral interrupt requests (pirqs) from several peripherals to the interrupt controller are ored together to generate a request to the cpu. there is an interrupt flag bit and an interrupt enable bit located in the peripheral for each event that can cause a peripheral interrupt request. there is also one pirq for each event. if an interrupt-causing event occurs in a peripheral, and the corresponding interrupt enable bit is set, the interrupt request from the peripheral to the interrupt controller is asserted. this interrupt request simply reflects the status of the peripheral's interrupt flag gated with the interrupt enable bit. when the interrupt flag is cleared, the interrupt request is cleared. some peripherals have the capability to make either a high-priority or a low-priority interrupt request. if a peripheral has this capability, the value of its interrupt priority bit is transmitted to the interrupt controller. the interrupt request continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by software. 2. at the upper level of the hierarchy, the ored pirqs generate interrupt (int) requests to the cpu. the request to the '24x cpu is a low-going pulse of 2 cpu clock cycles. the peripheral interrupt expansion (pie) controller generates an int pulse when any of the pirqs controlling that int go active. if any of the pirqs capable of asserting that cpu interrupt request are still active in the cycle following an interrupt acknowledge for that int, another int pulse is generated (an interrupt acknowledge clears the highest-priority pending pirq). which cpu interrupt requests get asserted by which peripheral interrupt requests, and the relative priority of each peripheral interrupt request, is defined in the interrupt controller and is not part of any of the peripherals. this is shown in table 10.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 30 post office box 1443 ? houston, texas 772511443 interrupt request structure (continued) table 10. 'f243/'f241 interrupt source priority and vectors interrupt name overall priority cpu interrupt and vector address bit position in pirqrx and piackrx peripheral interrupt vector (piv) maskable? source peripheral module description reset 1 rsn 0000h n/a n rs pin, watchdog reset from pin, watchdog timeout reserved 2 0026h n/a n cpu emulator trap nmi 3 nmi 0024h n/a n nonmaskable interrupt nonmaskable interrupt pdpint 4 0.0 0020h y ev power device protection interrupt pin adcint 5 0.1 0004h y adc adc interrupt in high-priority mode xint1 6 0.2 0001h y external interrupt logic external interrupt pins in high priority xint2 7 int1 0002h 0.3 0011h y external interrupt logic external interrupt pins in high priority spiint 8 0002h rxint 9 0.5 0006h y sci sci receiver interrupt in high-priority mode txint 10 0.6 0007h y sci sci transmitter interrupt in high-priority mode canmbint 11 canerint 12 cmp1int 13 0.9 0021h y ev compare 1 interrupt cmp2int 14 0.10 0022h y ev compare 2 interrupt cmp3int 15 0.11 0023h y ev compare 3 interrupt tpint1 16 int2 0.12 0027h y ev timer 1 period interrupt tcint1 17 0004h 0.13 0028h y ev timer 1 pwm interrupt tufint1 18 0.14 0029h y ev timer 1 underflow interrupt tofint1 19 0.15 002ah y ev timer 1 overflow interrupt tpint2 20 1.0 002bh y ev timer 2 period interrupt tcint2 21 int3 1.1 002ch y ev timer 2 pwm interrupt tufint2 22 0006h 1.2 002dh y ev timer 2 underflow interrupt tofint2 23 1.3 002eh y ev timer 2 overflow interrupt capint1 24 int4 1.4 0033h y ev capture 1 interrupt capint2 25 int4 0008h 1.5 0034h y ev capture 2 interrupt capint3 26 0008h 1.6 0035h y ev capture 3 interrupt
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 31 post office box 1443 ? houston, texas 772511443 interrupt request structure (continued) table 10.'f243/'f241 interrupt source priority and vectors (continued) interrupt name overall priority cpu interrupt and vector address bit position in pirqrx and piackrx peripheral interrupt vector (piv) maskable? source peripheral module description spiint 27 1.7 0005h y spi spi interrupt (low-priority) rxint 28 1.8 0006h y sci sci receiver interrupt (low-priority mode) txint 29 int5 000ah 1.9 0007h y sci sci transmitter interrupt (low-priority mode) canmbint 30 000ah 1.10 0040h y can can mailbox interrupt (low-priority mode) canerint 31 1.11 0041h y can can error interrupt (low-priority mode) adcint 32 1.12 0004h y adc adc interrupt (low-priority) xint1 33 int6 000ch 1.13 0001h y external interrupt logic external interrupt pins (low-priority mode) xint2 34 1.14 0011h y external interrupt logic external interrupt pins (low-priority mode) reserved 000eh n/a y cpu analysis interrupt trap n/a 0022h n/a n/a cpu trap instruction phantom interrupt vector n/a n/a 0000h n/a cpu phantom interrupt vector interrupt acknowledge when the cpu asserts its interrupt acknowledge, it simultaneously puts a value on the memory interface program address bus, which corresponds to the cpu interrupt being acknowledged (it does this because it is fetching the cpu interrupt vector from program memory, each int has a vector stored in a dedicated program memory address). this value is shown in table 10, column 3, cpu interrupt and vector address. the pie controller uses the cpu interrupt acknowledge to generate its internal signals to clear the current interrupt requests. interrupt vectors when the cpu receives an interrupt request (int), it does not know which peripheral event caused the request (pirq). to enable the cpu to distinguish between all of these events, a unique interrupt vector is generated in response to an active interrupt request getting acknowledged. this vector piv is loaded into the peripheral interrupt vector register (pivr) in the pie controller and can then be read by the cpu to generate a branch to the respective interrupt service routine (isr). in effect, there are two vector tables: a cpu vector table and a user-specified peripheral vector table. the cpu's vector table, which starts at 0000h, is used to get to the general interrupt service routine (gisr) in response to a cpu interrupt request (int). a user-specified peripheral vector table is employed to get to the event-specific interrupt service routine (sisr), corresponding to the event which caused the peripheral interrupt request (pirq). the code in the gisr should read the peripheral interrupt vector register (pivr) after saving any necessary context, and use this value piv to generate a branch to the sisr.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 32 post office box 1443 ? houston, texas 772511443 interrupt vectors (continued) the peripheral interrupt vectors (pivs) are stored in a table in the peripheral interrupt expansion controller. they can either be hard-coded (potentially rom), or register locations (ram), which are programmed by the reset service routine. the pivs are all implemented as hard-coded values on the 'f243/'f241 devices, according to table 10, column 5. phantom interrupt vector the phantom interrupt vector is an interrupt system integrity feature. if the cpu's interrupt acknowledge is asserted, but there is no associated peripheral interrupt request asserted, the phantom vector is used so that this fault is handled in a controlled manner. one way the phantom interrupt vector could be required is if the cpu executes a software interrupt instruction with an argument corresponding to a peripheral interrupt (usually int1int6). the other way would be if a peripheral made an interrupt request, but its interrupt request flag was cleared by software before the cpu acknowledged the request. in this case, there may be no peripheral interrupt request asserted to the interrupt controller, so the controller would not know which peripheral interrupt vector to load into the pivr. in these situations, the phantom interrupt vector is loaded into the pivr in lieu of a peripheral interrupt vector. software hierarchy there are two levels of interrupt service routine hierarchy: the general interrupt service routine (gisr), and the event-specific interrupt service routine (sisr). there is one gisr for each maskable prioritized request (int) to the cpu. this can perform necessary context saves before it fetches the piv from the pivr. this piv value is used to generate a branch to the sisr. there is one sisr for every interrupt request from a peripheral to the interrupt controller. the sisr performs the actions required in response to the peripheral interrupt request. nonmaskable interrupts the pie controller does not support expansion of nonmaskable interrupts. this is because an isr must read the peripheral interrupt vector from the pivr before interrupts are re-enabled. all interrupts are automatically disabled when any of the int1 int6 interrupts are serviced. if the pivr is not read before interrupts are re-enabled, another interrupt would be acknowledged and a new peripheral interrupt vector would be loaded into the pivr, causing permanent loss of the original peripheral interrupt vector. since, by their very nature, nonmaskable interrupts cannot be masked, they cannot be included in the interrupt expansion controller because they could cause the loss of peripheral interrupt vectors. interrupt operation sequence 1. an interrupt-generating event occurs in a peripheral. the interrupt flag (if) bit corresponding to that event is set in a register in the peripheral. if the appropriate interrupt enable (ie) bit is set, the peripheral generates an interrupt request to the pie controller by asserting its pirq. if the interrupt is not enabled in the peripheral register, the if remains set until cleared by software. if the interrupt is enabled at a later time, and the interrupt flag is still set, the pirq will immediately be asserted. the interrupt flag (if) in the peripheral register should be cleared by software only. if the if bit is not cleared after the respective interrupt service, future interrupts will not be recognized. 2. if no unacknowledged cpu interrupt request of the same priority level has previously been sent, the peripheral interrupt request, pirq, causes the pie controller to generate a cpu interrupt request pulse. this pulse is active low for 2 cpu clock cycles. 3. the interrupt request to the cpu sets the corresponding flag in the cpu's interrupt flag register, ifr. if the cpu interrupt has been enabled (by setting the appropriate bit in the cpu's interrupt mask register, imr), the cpu stops what it is doing. it then masks all other maskable interrupts by setting the intm bit, saves some context, clears the respective ifr bit, and starts executing the general interrupt service routine (gisr) for that interrupt priority level. the cpu generates an interrupt acknowledge automatically, which is accompanied by a value on the program address bus (pab) that corresponds to the interrupt priority level being responded to. these values are shown in table 10, column 3.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 33 post office box 1443 ? houston, texas 772511443 interrupt operation sequence (continued) 1. the pie controller decodes the pab value and generates an internal peripheral interrupt acknowledge to load the piv into the pivr. the appropriate peripheral interrupt vector (or the phantom interrupt vector), is referenced from the table stored in the pie controller. 2. when the gisr has completed any necessary context saves, it reads the pivr and uses the interrupt vector as a target (or to generate a target) for a branch to the event-specific interrupt service routine (sisr) for the interrupt event which occurred in the peripheral. interrupts must not be re-enabled until the pivr has been read; otherwise, its contents can get overwritten by a subsequent interrupt. external interrupts the 'f243/'f241 devices have four external interrupts. these interrupts include: xint1. the xint1 control register (at 7070h) provides control and status for this interrupt. xint1 can be used as a high-priority (level 1) or low-priority (level 6) maskable interrupt or as a general-purpose i/o pin. xint1 can also be programmed to trigger an interrupt on either the rising or the falling edge. xint2. the xint2 control register (at 7071h) provides control and status for this interrupt. xint2 can be used as a high-priority (level 1) or low-priority (level 6) maskable interrupt or a general-purpose i/o pin. xint2 can also be programmed to trigger an interrupt on either the rising or the falling edge. nmi . this is a nonmaskable external interrupt. pdpint . this interrupt is provided for safe operation of power converters and motor drives controlled by the 'f243/'f241. this maskable interrupt can put the timers and pwm output pins in high-impedance states and inform the cpu in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive temperature rise. pdpint is a level 1 interrupt. table 11 is a summary of the external interrupt capability of the 'f243/'f241. table 11. external interrupt types and functions external interrupt control register name control register address maskable? xint1 xint1cr 7070h yes (level 1 or 6) xint2 xint2cr 7071h yes (level 1 or 6) nmi e e no pdpint evimra 742ch yes (level 1)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 34 post office box 1443 ? houston, texas 772511443 clock generation the 'f243/'f241 devices have an on-chip, (x4) pll-based clock module. this module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. the only external component necessary for this module is a fundamental crystal. the atimes 4o (x4) option for the 'f243/'f241 pll is fixed and cannot be changed. the pll-based clock module provides two modes of operation: crystal-operation this mode allows the use of a 5-mhz external reference crystal to provide the time base to the device. external clock source operation this mode allows the internal oscillator to be bypassed. the device clocks are generated from an external clock source input on the xtal1/clkin pin. in this case, an external oscillator clock is connected to the xtal1/clkin pin. the clock module includes two external pins: 1. xtal1/clkin clock source/crystal input 2. xtal2 output to crystal xtal2 xtal1/clkin x4 pll xtal osc cpuclk figure 7. pll clock module block diagram low-power modes the '24x has an idle instruction. when executed, the idle instruction stops the clocks to all circuits in the cpu, but the clock output from the cpu continues to run. with this instruction, the cpu clocks can be shut down to save power while the peripherals (clocked with clkout) continue to run. the cpu exits the idle state if it is reset, or, if it receives an interrupt request. clock domains all '24x-based devices have two clock domains: 1. cpu clock domain consists of the clock for most of the cpu logic 2. system clock domain consists of the peripheral clock (which is derived from clkout of the cpu) and the clock for the interrupt logic in the cpu. when the cpu goes into idle mode, the cpu clock domain is stopped while the system clock domain continues to run. this mode is also known as idle1 mode. the '24x cpu also contains support for a second idle mode, idle2. by asserting idle2 to the '24x cpu, both the cpu clock domain and the system clock domain are stopped, allowing further power savings. a third low-power mode, halt mode, the deepest, is possible if the oscillator and wdclk are also shut down when in idle2 mode.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 35 post office box 1443 ? houston, texas 772511443 low-power modes (continued) two control bits, lpm(1) and lpm(0), specify which of the three possible low-power modes is entered when the idle instruction is executed (see table 12). these bits are located in the system control and status register (scsr) described in the tms320c241/c242/c243 dsp controllers cpu, system, instruction set, and peripherals reference guide (literature number spru276). table 12. low-power modes summary low-power mode lpmx bits scsr[12:13] cpu clock domain system clock domain wdclk status pll status osc status exit condition cpu running normally xx on on on on on e idle1 (lpm0) 00 off on on on on peripheral interrupt, external interrupt, reset idle2 (lpm1) 01 off off on on on wakeup interrupts, external interrupt, reset halt (lpm2) {pll/osc power down} 1x off off off off off reset only wakeup from low-power modes reset a reset (from any source) causes the device to exit any of the idle modes. if the device is halted, the reset will first start the oscillator, and there can be a delay while the oscillator powers up before clocks are generated to initiate the cpu reset sequence. external interrupts the external interrupts, xintx, can cause the device to exit any of the low-power modes, except halt. if the device is in idle2 mode, the synchronous logic connected to the external interrupt pins is bypassed with combinatorial logic which recognizes the interrupt on the pin, starts the clocks, and then allows the clocked logic to generate an interrupt request to the pie controller. note that in table 12, external interrupts include pdpint . wakeup interrupts certain peripherals (for example, the can wakeup interrupt which can assert the can error interrupt request even when there are no clocks running) can have the capability to start the device clocks and then generate an interrupt in response to certain external events, for example, activity on a communication line. peripheral interrupts all peripheral interrupts, if enabled locally and globally, can cause the device to exit idle1 mode.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 36 post office box 1443 ? houston, texas 772511443 peripheral interrupts (continued) nmi external-interrupt logic reset logic reset signal wake-up signal to cpu 2 xint2 xint1 peripheral interrupts external reset (rs pin) watchdog timer module (wake-up signal) m u x 2 the cpu can exit halt mode (lpm2) with a reset only. figure 8. waking up the device from power down
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 37 post office box 1443 ? houston, texas 772511443 functional block diagram of the '24x dsp cpu 32 16 data bus 16 oscale (07) d15d0 a15a0 16 16 16 32 32 accl(16) acch(16) c 32 calu(32) 32 32 mux iscale (016) 16 mux preg(32) multiplier treg0(16) mux 16 16 mux b1 (256 16) b2 (32 16) daram b0 (256 16) daram 7 lsb from ir mux dp(9) 9 9 mux 16 16 arau(16) 16 3 3 3 3 arb(3) arp(3) program bus 16 16 16 16 ar7(16) ar6(16) ar5(16) ar3(16) ar2(16) ar1(16) ar0(16) stack 8 16 pc mux nmi we w/r 16 clkin/x2 clkout x1 2 xint[12] mp/mc rs xf br ready strb r/w ps ds is control data bus program bus data bus ar4(16) 16 mux mux data/prog 16 pscale (6, 0, 1, 4) 16 data 32 16 16 16 16 16 flash eeprom/ rom mux mux npar par mstack program control (pctrl) memory map register imr (16) ifr (16) greg (16) 16 program bus notes: a. symbol descriptions appear in table 13 and table 14. b. for clarity, the data and program buses are shown as single buses although they include address and data bits.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 38 post office box 1443 ? houston, texas 772511443 '24x legend for the internal hardware table 13. legend for the '24x internal hardware symbol name description acc accumulator 32-bit register that stores the results and provides input for subsequent calu operations. also includes shift and rotate capabilities arau auxiliary register arithmetic unit an unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs aux regs auxiliary registers 07 these 16-bit registers are used as pointers to anywhere within the data space address range. they are operated upon by the arau and are selected by the auxiliary register pointer (arp). ar0 can also be used as an index value for ar updates of more than one and as a compare value to ar. br bus request signal br is asserted during access of the external global data memory space. ready is asserted to the device when the global data memory is available for the bus transaction. br can be used to extend the data memory address space by up to 32k words. c carry register carry output from calu. c is fed back into the calu for extended arithmetic operation. the c bit resides in status register 1 (st1), and can be tested in conditional instructions. c is also used in accumulator shifts and rotates. calu central arithmetic logic unit 32-bit-wide main arithmetic logic unit for the tms320c2xx core. the calu executes 32-bit operations in a single machine cycle. calu operates on data coming from iscale or pscale with data from acc, and provides status results to pctrl. daram dual-access ram if the on-chip ram configuration control bit (cnf) is set to 0, the reconfigurable data dual-access ram (daram) block b0 is mapped to data space; otherwise, b0 is mapped to program space. blocks b1 and b2 are mapped to data memory space only, at addresses 030003ff and 0060007f, respectively. blocks 0 and 1 contain 256 words, while block 2 contains 32 words. dp data memory page pointer the 9-bit dp register is concatenated with the seven least significant bits (lsbs) of an instruction word to form a direct memory address of 16 bits. dp can be modified by the lst and ldp instructions. greg global memory allocation register greg specifies the size of the global data memory space. imr interrupt mask register imr individually masks or enables the seven interrupts. ifr interrupt flag register the 7-bit ifr indicates that the tms320c2xx has latched an interrupt from one of the seven maskable interrupts. int# interrupt traps a total of 32 interrupts by way of hardware and/or software are available. iscale input data-scaling shifter 16- to 32-bit barrel left-shifter. iscale shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. mpy multiplier 16 16-bit multiplier to a 32-bit product. mpy executes multiplication in a single cycle. mpy operates either signed or unsigned 2s-complement arithmetic multiply. mstack micro stack mstack provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. mux multiplexer multiplexes buses to a common input npar next program address register npar holds the program address to be driven out on the pab on the next cycle. oscale output data-scaling shifter 16- to 32-bit barrel left-shifter. oscale shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data bus (dweb). par program address register par holds the address currently being driven on pab for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle. pc program counter pc increments the value from npar to provide sequential addresses for instruction-fetching and sequential data-transfer operations. pctrl program controller pctrl decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 39 post office box 1443 ? houston, texas 772511443 '24x legend for the internal hardware (continued) table 13. legend for the '24x internal hardware (continued) symbol name description preg product register 32-bit register holds results of 16 16 multiply pscale product-scaling shifter 0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. the left-shift options are used to manage the additional sign bits resulting from the 2s-complement multiply. the right-shift option is used to scale down the number to manage overflow of product accumulation in the calu. pscale resides in the path from the 32-bit product shifter and from either the calu or the data-write data bus (dweb), and requires no cycle overhead. stack stack stack is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. the 'c24x stack is 16-bit wide and eight-level deep. treg temporary register 16-bit register holds one of the operands for the multiply operations. treg holds the dynamic shift count for the lact, addt, and subt instructions. treg holds the dynamic bit position for the bitt instruction. 'f243/'f241 dsp core cpu the tms320x24x devices use an advanced harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures e program and data e for full-speed execution. this multiple bus structure allows data and instructions to be read simultaneously. instructions support data transfers between program memory and data memory. this architecture permits coefficients that are stored in program memory to be read in ram, thereby eliminating the need for a separate coefficient rom. this, coupled with a four-deep pipeline, allows the 'f243/'f241 devices to execute most instructions in a single cycle. status and control registers two status registers, st0 and st1, contain the status of various conditions and modes. these registers can be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines. the load status register (lst) instruction is used to write to st0 and st1. the store status register (sst) instruction is used to read from st0 and st1 e except for the intm bit, which is not affected by the lst instruction. the individual bits of these registers can be set or cleared when using the setc and clrc instructions. figure 9 shows the organization of status registers st0 and st1, indicating all status bits contained in each. several bits in the status registers are reserved and are read as logic 1s. table 14 lists status register field definitions. 15 13 12 11 10 9 8 0 st0 arp ov ovm 1 intm dp 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st1 arb cnf tc sxm c 1 1 1 1 xf 1 1 pm figure 9. status and control register organization table 14. status register field definitions field function arb auxiliary register pointer buffer. when the arp is loaded into st0, the old arp value is copied to the arb except during an lst instruction. when the arb is loaded by way of an lst #1 instruction, the same value is also copied to the arp. arp auxiliary register (ar) pointer. arp selects the ar to be used in indirect addressing. when the arp is loaded, the old arp valu e is copied to the arb register. arp can be modified by memory-reference instructions when using indirect addressing, and by the larp, mar, and lst instructions. the arp is also loaded with the same value as arb when an lst #1 instruction is executed.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 40 post office box 1443 ? houston, texas 772511443 table 14. status register field definitions (continued) field function c carry bit. c is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. otherwise, c is reset after an addition or set after a subtraction, except if the instruction is add or sub with a 16-bit shift . in these cases, the add can only set and the sub only reset the carry bit, but cannot affect it otherwise. the single-bit shift and rota te instructions also affect c, as well as the setc, clrc, and lst #1 instructions. branch instructions have been provided to branc h on the status of c. c is set to 1 on a reset. cnf on-chip ram configuration control bit. if cnf is set to 0, the reconfigurable data dual-access ram blocks are mapped to data space; otherwise, they are mapped to program space. the cnf can be modified by the setc cnf, clrc cnf, and lst #1 instructions. rs sets the cnf to 0. dp data memory page pointer. the 9-bit dp register is concatenated with the seven lsbs of an instruction word to form a direct memory address of 16 bits. dp can be modified by the lst and ldp instructions. intm interrupt mode bit. when intm is set to 0, all unmasked interrupts are enabled. when set to 1, all maskable interrupts are disa bled. intm is set and reset by the setc intm and clrc intm instructions. rs also sets intm. intm has no effect on the unmaskable rs and nmi interrupts. note that intm is unaffected by the lst instruction. this bit is set to 1 by reset. it is also set to 1 wh en a maskable interrupt trap is taken. ov overflow flag bit. as a latched overflow signal, ov is set to 1 when overflow occurs in the arithmetic logic unit (alu). once a n overflow occurs, the ov remains set until a reset, bcnd/d on ov/nov, or lst instructions clear ov. ovm overflow mode bit. when ovm is set to 0, overflowed results overflow normally in the accumulator. when set to 1, the accumulato r is set to either its most positive or negative value upon encountering an overflow. the setc and clrc instructions set and rese t this bit, respectively. lst can also be used to modify the ovm. pm product shift mode. if these two bits are 00, the multiplier's 32-bit product is loaded into the alu with no shift. if pm = 01, the preg output is left-shifted one place and loaded into the alu, with the lsb zero-filled. if pm = 10, preg output is left-shifted by four bits and loaded into the alu, with the lsbs zero-filled. pm = 11 produces a right shift of six bits, sign-extended. note that t he preg contents remain unchanged. the shift takes place when transferring the contents of the preg to the alu. pm is loaded by the spm and lst #1 instructions. pm is cleared by rs . sxm sign-extension mode bit. sxm = 1 produces sign extension on data as it is passed into the accumulator through the scaling shift er. sxm = 0 suppresses sign extension. sxm does not affect the definitions of certain instructions; for example, the adds instructi on suppresses sign extension regardless of sxm. sxm is set by the setc sxm and reset by the clrc sxm instructions, and can be loaded by the lst #1 instruction. sxm is set to 1 by reset. tc test/control flag bit. tc is affected by the bit, bitt, cmpr, lst #1, and norm instructions. tc is set to a 1 if a bit tested b y bit or bitt is a 1, if a compare condition tested by cmpr exists between ar (arp) and ar0, if the exclusive-or function of the two most significant bits (msbs) of the accumulator is true when tested by a norm instruction. the conditional branch, call, and re turn instructions can execute based on the condition of tc. xf xf pin status bit. xf indicates the state of the xf pin, a general-purpose output pin. xf is set by the setc xf and reset by th e clrc xf instructions. xf is set to 1 by reset. central processing unit the tms320x24x central processing unit (cpu) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (calu), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. this section describes the cpu components and their functions. the functional block diagram shows the components of the cpu. input scaling shifter the tms320x24x provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the calu. this shifter operates as part of the path of data coming from program or data space to the calu and requires no cycle overhead. it is used to align the 16-bit data coming from memory to the 32-bit calu. this is necessary for scaling arithmetic as well as aligning masks for logical operations. the scaling shifter produces a left shift of 0 to 16 on the input data. the lsbs of the output are filled with zeros; the msbs can either be filled with zeros or sign-extended, depending upon the value of the sxm bit (sign-extension mode) of status register st1. the shift count is specified by a constant embedded in the status and control registers (continued)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 41 post office box 1443 ? houston, texas 772511443 input scaling shifter (continued) instruction word or by a value in treg. the shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. the treg base shift allows the scaling factor to be adaptable to the system's performance. multiplier the tms320x24x devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. all multiply instructions, except the mpyu (multiply unsigned) instruction, perform a signed multiply operation. that is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. there are two registers associated with the multiplier, as follow: 16-bit temporary register (treg) that holds one of the operands for the multiplier 32-bit product register (preg) that holds the product four product shift modes (pm) are available at the preg output (pscale). these shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. the pm field of status register st1 specifies the pm shift mode, as shown in table 15. table 15. pscale product shift modes pm shift description 00 no shift product feed to calu or data bus with no shift 01 left 1 removes the extra sign bit generated in a 2s-complement multiply to produce a q31 product 10 left 4 removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a q31 product when using the multiply by a 13-bit constant 11 right 6 scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow the product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (mpy instruction). a four-bit shift is used in conjunction with the mpy instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. finally, the output of preg can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. the lt (load treg) instruction normally loads treg to provide one operand (from the data bus), and the mpy (multiply) instruction provides the second operand (also from the data bus). a multiplication also can be performed with a 13-bit immediate operand when using the mpy instruction. then a product is obtained every two cycles. when the code is executing multiple multiplies and product sums, the cpu supports the pipelining of the treg load operations with calu operations using the previous product. the pipeline operations that run in parallel with loading the treg include: load acc with preg (ltp); add preg to acc (lta); add preg to acc and shift treg input data (dmov) to next address in data memory (ltd); and subtract preg from acc (lts). two multiply/accumulate instructions (mac and macd) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. the data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. this facilitates single-cycle multiply/accumulates when used with the repeat (rpt) instruction. in these instructions, the coefficient addresses are generated by program address generation (pagen) logic, while the data addresses are generated by data address generation (dagen) logic. this allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. the macd instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 42 post office box 1443 ? houston, texas 772511443 multiplier (continued) the mpyu instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. the unsigned contents of treg are multiplied by the unsigned contents of the addressed data memory location, with the result placed in preg. this process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. the sqra (square / add) and sqrs (square / subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. after the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (preg). the product from preg can be transferred to the calu or to data memory by way of the sph (store product high) and spl (store product low) instructions. note: the transfer of preg to either the calu or data bus passes through the pscale shifter, and therefore is affected by the product shift mode defined by pm. this is important when saving preg in an interrupt-service-routine context save as the pscale shift effects cannot be modeled in the restore operation. preg can be cleared by executing the mpy #0 instruction. the product register can be restored by loading the saved low half into treg and executing a mpy #1 instruction. the high half, then, is loaded using the lph instruction. central arithmetic logic unit the tms320x24x central arithmetic logic unit (calu) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. this alu is referred to as central to differentiate it from a second alu used for indirect-address generation called the auxiliary register arithmetic unit (arau). once an operation is performed in the calu, the result is transferred to the accumulator (acc) where additional operations, such as shifting, can occur. data that is input to the calu can be scaled by iscale when coming from one of the data buses (drdb or prdb) or scaled by pscale when coming from the multiplier. the calu is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. in addition to the usual arithmetic instructions, the calu can perform boolean operations, facilitating the bit manipulation ability required for a high-speed controller. one input to the calu is always provided from the accumulator, and the other input can be provided from the product register (preg) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the acc). after the calu has performed the arithmetic or logical operation, the result is stored in the accumulator. the tms320x24x devices support floating-point operations for applications requiring a large dynamic range. the norm (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. the four bits of the treg define a variable shift through the scaling shifter for the lact/addt/subt (load/add to /subtract from accumulator with shift specified by treg) instructions. these instructions are useful in floating-point arithmetic where a number needs to be denormalized e that is, floating-point to fixed-point conversion. they are also useful in execution of an automatic gain control (agc) going into a filter. the bitt (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four lsbs of treg. the calu overflow saturation mode can be enabled/disabled by setting/resetting the ovm bit of st0. when the calu is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. the value of the accumulator at saturation is 07fffffffh (positive) or 080000000h (negative). if the ovm (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (note that logical operations cannot result in overflow.) the calu can execute a variety of branch instructions that depend on the status of the calu and the accumulator. these instructions can be executed conditionally based on any meaningful combination of these status bits. for overflow management, these conditions include the ov (branch on overflow) and eq (branch on accumulator equal to zero). in addition, the bacc (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). bit test instructions (bit and bitt), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 43 post office box 1443 ? houston, texas 772511443 central arithmetic logic unit (continued) the calu also has an associated carry bit that is set or reset depending on various operations within the device. the carry bit allows more efficient computation of extended-precision products and additions or subtractions. it also is useful in overflow management. the carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. it is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. the addc (add to accumulator with carry) and subb (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. the one exception to the operation of the carry bit is in the use of add with a shift count of 16 (add to high accumulator) and sub with a shift count of 16 (subtract from high accumulator) instructions. this case of the add instruction can set the carry bit only if a carry is generated, and this case of the sub instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. two conditional operands, c and nc, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. the setc, clrc, and lst #1 instructions also can be used to load the carry bit. the carry bit is set to one on a hardware reset. accumulator the 32-bit accumulator is the registered output of the calu. it can be split into two 16-bit segments for storage in data memory. shifters at the output of the accumulator provide a left shift of 0 to 7 places. this shift is performed while the data is being transferred to the data bus for storage. the contents of the accumulator remain unchanged. when the post-scaling shifter is used on the high word of the accumulator (bits 1631), the msbs are lost and the lsbs are filled with bits shifted in from the low word (bits 015). when the post-scaling shifter is used on the low word, the lsbs are zero-filled. the sfl and sfr (in-place one-bit shift to the left / right) instructions and the rol and ror (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. the sxm bit affects the definition of the sfr (shift accumulator right) instruction. when sxm = 1, sfr performs an arithmetic right shift, maintaining the sign of the accumulator data. when sxm = 0, sfr performs a logical shift, shifting out the lsbs and shifting in a zero for the msb. the sfl (shift accumulator left) instruction is not affected by the sxm bit and behaves the same in both cases, shifting out the msb and shifting in a zero. repeat (rpt) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (arau) the 'x243/'x241 provides a register file containing eight auxiliary registers (ar0 ar7). the auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. these registers are referenced with a 3-bit auxiliary register pointer (arp) that is loaded with a value from 0 through 7, designating ar0 through ar7, respectively. the auxiliary registers and the arp can be loaded from data memory, the acc, the product register, or by an immediate operand defined in the instruction. the contents of these registers also can be stored in data memory or used as inputs to the calu. the auxiliary register file (ar0 ar7) is connected to the arau. the arau can autoindex the current auxiliary register while the data memory location is being addressed. indexing either by 1 or by the contents of the ar0 register can be performed. as a result, accessing tables of information does not require the calu for address manipulation; therefore, the calu is free for other operations in parallel. internal memory the tms320x24x devices are configured with the following memory modules: dual-access random-access memory (daram) flash
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 44 post office box 1443 ? houston, texas 772511443 internal memory (continued) dual-access ram (daram) there are 544 words 16 bits of daram on the 'x243/'x241 device. the 'x243/'x241 daram allows writes to and reads from the ram in the same cycle. the daram is configured in three blocks: block 0 (b0), block 1 (b1), and block 2 (b2). block 1 contains 256 words and block 2 contains 32 words, and both blocks are located only in data memory space. block 0 contains 256 words, and can be configured to reside in either data or program memory space. the setc cnf (configure b0 as data memory) and clrc cnf (configure b0 as program memory) instructions allow dynamic configuration of the memory maps through software. when using on-chip ram, or high-speed external memory, the 'x243/'x241 runs at full speed with no wait states. the ability of the daram to allow two accesses to be performed in one cycle, coupled with the parallel nature of the 'x243/'x241 architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. externally, the ready line can be used to interface the 'x243/'x241 to slower, less expensive external memory. downloading programs from slow off-chip memory to on-chip ram can speed processing while cutting system costs. flash eeprom flash eeprom provides an attractive alternative to masked program rom. like rom, flash is nonvolatile. however, it has the advantage of ain-targeto reprogrammability. the 'f243/'f241 incorporates one 8k 16-bit flash eeprom module in program space. this type of memory expands the capabilities of the 'f243/'f241 in the areas of prototyping, early field-testing, and single-chip applications. unlike most discrete flash memory, the 'f243/'f241 flash does not require a dedicated state machine, because the algorithms for programming and erasing the flash are executed by the dsp core. this enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. for production programming, the ieee standard 1149.1 2 (jtag) scan port provides easy access to the on-chip ram for downloading the algorithms and flash code. other key features of the flash include zero-wait-state access rate and single 5-v power supply. before programming, the flash eeprom module generates the necessary voltages internally, making it unnecessary to provide the programming or erase voltages externally. an erased bit in the flash is read as a logic 1, and a programmed bit is read as a logic 0. the flash requires a block-erase of the entire 8k module; however, any combination of bits can be programmed. the following four algorithms are required for flash operations: clear, erase, flash-write, and program. for an explanation of these algorithms and a complete description of the flash eeprom, see the tms320f20x/f24x dsp embedded flash memory technical reference (literature number spru282). flash serial loader/utilities the on-chip flash is shipped with a serial bootloader code programmed at the following addresses: 000000ffh. all other flash memory locations are in an erased state. the serial bootloader can be used to load flash-programming algorithms or code to any destination ram through the on-chip serial communications interface (sci). refer to the tms320f240 serial bootloader application note (located at ftp://www.ti.com/ ) to understand on-chip flash programming using the serial bootloader code. (choose /pub/tms320bbs/c24xfiles at the main ftp directory to locate the f240boot.pdf file.) the latest tms320f243/241 flash utilities should be available at http://www.ti.com which is the external ti web site. 2 ieee standard 1149.11990, ieee standard test access port.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 45 post office box 1443 ? houston, texas 772511443 peripherals the integrated peripherals of the tms320x24x are described in the following subsections: external memory interface ('f243 only) event-manager (ev2) module analog-to-digital converter (adc) module serial peripheral interface (spi) module serial communications interface (sci) module controller area network (can) module watchdog (wd) timer module external memory interface ('f243 only) the tms320f243 can address up to 64k 16 words of memory (or registers) in each of the program, data, and i / o spaces. on-chip memory, when enabled, occupies some of this off-chip range. in data space, the high 32k words can be mapped dynamically either locally or globally using the global memory allocation register (greg) as described in the tms320c241/c242/c243 dsp controllers cpu, system, instruction set, and peripherals reference guide (literature number spru276). access to a data-memory location, that is mapped as global, asserts the br pin low. the cpu of the tms320f243 schedules a program fetch, data read, and data write on the same machine cycle. this is because from on-chip memory, the cpu can execute all three of these operations in the same cycle. however, the external interface multiplexes the internal buses to one address and one data bus. the external interface sequences these operations to complete first the data write, then the data read, and finally the program read. the 'f243 supports a wide range of system interfacing requirements. program, data, and i/o address spaces provide interface to memory and i/o, thereby maximizing system throughput. the full 16-bit address and data bus, along with the ps , ds , and is space-select signals, allow addressing of 64k 16-bit words in program, data, and i/o space. since on-chip peripheral registers occupy positions of data-memory space, the externally addressable data-memory space is 32k 16-bit words. i/o design is simplified by having i/o treated the same way as memory. i/o devices are accessed in the i/o address space using the processor's external address and data buses in the same manner as memory-mapped devices. the 'f243 external parallel interface provides various control signals to facilitate interfacing to the device. the r/w output signal is provided to indicate whether the current cycle is a read or a write. the strb output signal provides a timing reference for all external cycles. for convenience, the device also provides the rd and the we output signals, which indicate a read and a write cycle, respectively, along with timing information for those cycles. the availability of these signals minimizes external gating necessary for interfacing external devices to the 'f243. the bus request (br ) signal is used in conjunction with other 'f243 interface signals to arbitrate external global memory accesses. global memory is external data memory space in which the br signal is asserted at the beginning of the access. when an external global memory device receives the bus request, it responds by asserting the ready signal after the global memory access is arbitrated and the global access is completed. the tms320f243 supports zero-wait-state reads on the external interface. however, to avoid bus conflicts, writes take two cycles. this allows the tms320f243 to buffer the transition of the data bus from input to output (or output to input) by a half cycle. in most systems, tms320f243 ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 46 post office box 1443 ? houston, texas 772511443 external memory interface ('f243 only) (continued) wait states can be generated when accessing slower external resources. the wait states operate on machine-cycle boundaries and are initiated either by using the ready pin or using the software wait-state generator. ready pin can be used to generate any number of wait states. when using the ready pin to communicate with slower devices, the 'f243 processor waits until the slower device completes its function and signals the processor by way of the ready line. once a ready indication is provided back to the 'f243 from the external device, execution continues. for external wait states using the ready pin, the on-chip wait-state generator must be programmed to generate at least one wait state. wait-state generation ('f243 only) wait-state generation is incorporated in the 'f243 without any external hardware for interfacing the 'f243 with slower off-chip memory and i/o devices. adding wait states lengthens the time the cpu waits for external memory or an external i/o port to respond when the cpu reads from or writes to that external memory or i/o port. specifically, the cpu waits one extra cycle (one clkout cycle) for every wait state. the wait states operate on clkout cycle boundaries. to avoid bus conflicts, writes from the 'f243 always take at least two clkout cycles. the 'f243 offers two options for generating wait states: ready signal. with the ready signal, you can externally generate any number of wait states. the ready pin has no effect on accesses to internal memory. on-chip wait-state generator. with this generator, you can generate zero to seven wait states. generating wait states with the ready signal when the ready signal is low, the 'f243 waits one clkout cycle and then checks ready again. the 'f243 will not continue executing until the ready signal is driven high; therefore, if the ready signal is not used, it should be pulled high. the ready pin can be used to generate any number of wait states. however, when the 'f243 operates at full speed, it may not respond fast enough to provide a ready-based wait state for the first cycle. for extended wait states using external ready logic, the on-chip wait-state generator should be programmed to generate at least one wait state. generating wait states with the 'f243 on-chip software wait-state generator the software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip memory space (program, data, or i/o), regardless of the state of the ready signal. these zero to seven wait states are controlled by the wait-state generator register (wsgr) (i/o ffffh). for more detailed information on the wsgr and associated bit functions, refer to the tms320c241/c242/c243 dsp controllers cpu, system, instructio2n set, and peripherals reference guide (literature number spru276).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 47 post office box 1443 ? houston, texas 772511443 event-manager (ev2) module the event-manager module includes general-purpose (gp) timers, full compare/pwm units, capture units, and quadrature-encoder pulse (qep) circuits. figure 10 shows the functions of the event manager. dsp core data bus addr bus ev control registers and control logic gp timer 1 compare full compare units gp timer 2 compare gp timer 2 mux capture units 16 16 16 16 16 16 16 gp timer 1 3 int2, 3, 4 2 tclkin tdir adc start t1pwm svpwm state machine deadband units output logic 33 pwm1 3 pwm6 output logic 3 t2pwm 2 2 2 qep circuit to control logic clock dir cap1 / qep0 cap2 / qep1 cap3 16 16 16 16 internal clock reset output logic 16 16 16 16 figure 10. event-manager block diagram
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 48 post office box 1443 ? houston, texas 772511443 general-purpose (gp) timers there are two gp timers on the tms320x24x. the gp timer x (for x = 1 or 2) includes: a 16-bit timer, up-/down-counter, txcnt, for reads or writes a 16-bit timer-compare register, txcmpr (double-buffered with shadow register), for reads or writes a 16-bit timer-period register, txpr (double-buffered with shadow register), for reads or writes a 16-bit timer-control register,txcon, for reads or writes selectable internal or external input clocks a programmable prescaler for internal or external clock inputs control and interrupt logic, for four maskable interrupts: underflow , overflow , timer compare , and period interrupts a selectable direction input pin (tdir) (to count up or down when directional up- / down-count mode is selected) the gp timers can be operated independently or synchronized with each other. the compare register associated with each gp timer can be used for compare function and pwm-waveform generation. there are three continuous modes of operations for each gp timer in up- or up / down-counting operations. internal or external input clocks with programmable prescaler is used for each gp timer. gp timers also provide the time base for the other event-manager submodules: gp timer 1 for all the compares and pwm circuits, gp timer 2/1 for the capture units and the quadrature-pulse counting operations. double-buffering of the period and compare registers allows programmable change of the timer (pwm) period and the compare/pwm pulse width as needed. full-compare units there are three full-compare units on tms320x24x. these compare units use gp timer1 as the time base and generate six outputs for compare and pwm-waveform generation using programmable deadband circuit. the state of each of the six outputs is configured independently. the compare registers of the compare units are double-buffered, allowing programmable change of the compare/pwm pulse widths as needed. programmable deadband generator the deadband generator circuit includes three 8-bit counters and an 8-bit compare register. desired deadband values (from 0 to 24 s) can be programmed into the compare register for the outputs of the three compare units. the deadband generation can be enabled/disabled for each compare unit output individually. the deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. the output states of the deadband generator are configurable and changeable as needed by way of the double-buffered actr register. pwm waveform generation up to 8 pwm waveforms (outputs) can be generated simultaneously by tms320x24x: three independent pairs (six outputs) by the three full-compare units with programmable deadbands , and two independent pwms by the gp-timer compares.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 49 post office box 1443 ? houston, texas 772511443 pwm characteristics characteristics of the pwms are as follows: 16-bit registers programmable deadband for the pwm output pairs, from 0 to 24 s minimum deadband width of 50 ns change of the pwm carrier frequency for pwm frequency wobbling as needed change of the pwm pulse widths within and after each pwm period as needed external-maskable power and drive-protection interrupts pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector pwm waveforms minimized cpu overhead using auto-reload of the compare and period registers capture unit the capture unit provides a logging function for different events or transitions. the values of the gp timer 2 counter are captured and stored in the two-level fifo stacks when selected transitions are detected on capture input pins, capx for x = 1, 2, or 3. the capture unit of the tms320x24x consists of three capture circuits. capture units include the following features: one 16-bit capture control register, capcon (r/w) one 16-bit capture fifo status register, capfifo (8 msbs are read-only, 8 lsbs are write-only) selection of gp timer 2 as the time base three 16-bit 2-level-deep fifo stacks, one for each capture unit three schmitt-triggered capture input pins cap1, cap2, and cap3, one input pin per each capture unit. [all inputs are synchronized with the device (cpu) clock. in order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. the input pins cap1 and cap2 can also be used as qep inputs to the qep circuit.] user-specified transition (rising edge, falling edge, or both edges) detection three maskable interrupt flags, one for each capture unit quadrature-encoder pulse (qep) circuit two capture inputs (cap1 and cap2) can be used to interface the on-chip qep circuit with a quadrature encoder pulse. full synchronization of these inputs is performed on-chip. direction or leading-quadrature pulse sequence is detected, and gp timer 2 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 50 post office box 1443 ? houston, texas 772511443 analog-to-digital converter (adc) module a simplified functional block diagram of the adc module is shown in figure 11. the adc module consists of a 10-bit adc with a built-in sample-and-hold (s / h) circuit. a total of 8 analog input channels is available on the 'f243/'f241. eight analog inputs are provided by way of an 8-to-1 analog multiplexer. maximum total conversion time for each adc unit is 1 s. reference voltage for the adc module is 05 v and is supplied externally. functions of the adc module include: the adc unit can perform single or continuous s / h and conversion operations. when in continuous conversion mode, the adc generates two results every 1700 ns (with a 20-mhz clock and a prescale factor of 1). these two results can be two separate analog inputs. two 2-level-deep fifo result registers conversion can be started by software, an external signal transition on a device pin (adcsoc), or by certain event manager events. the adc control register is double-buffered (with a shadow register) and can be written to at any time. a new conversion can start either immediately or when the previous conversion process is completed. in single-conversion mode, at the end of each conversion, an interrupt flag is set and the peripheral interrupt request (pirq) is generated if it is unmasked/enabled. the result of previous conversions stored in data registers will be lost when a third result is stored in the 2-level-deep data fifo. a/d overview the apseudoo dual adc is based around a 10-bit string/capacitor converter with the switched capacitor string providing an inherent s / h function. (note: there is only one converter with only one inherent s/h circuit.) this peripheral behaves as though there are two analog converters, adc #1 and adc #2, but in fact, it uses only one converter. this feature makes the a/d software compatible with the c240's a/d and also allows two values (e.g., voltage and current) to be converted almost simultaneoulsy with one conversion request. v cca and v ssa pins must be connected to 5 v and analog ground, respectively. standard isolation techniques must be used while applying power to the adc module. the adc module, shown in figure 11, has the following features: up to 8 analog inputs, adcin00adcin07. the results from converting the inputs adcin00adcin07 are placed in one of the adcfifo results registers (see table 16). the digital value of the input analog voltage is derived by: digital value 1024 input analog voltage v refhi v reflo almost simultaneous measurement of two analog inputs, 1700 ns apart single conversion and continuous conversion modes conversion can be started by software, an internal event, and/or an external event. v refhi and v reflo (high- and low-voltage) reference inputs two-level-deep digital result registers that contain the digital vaules of completed conversions two programmable adc module control registers (see table 16) programmable clock prescaler interrupt or polled operation
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 51 post office box 1443 ? houston, texas 772511443 a/d overview (continued) adcin00 adcin01 adcin07 analog switch analog switch analog switch analog switch control registers program clock prescaler control logic adcin02 data reg. 1 2-level-deep fifo (adcfifo1) data reg. 2 2-level-deep fifo (adcfifo2) timing and control logic successive approximation register 5-bit resistor string 5-bit capacitor array comparator ain v ssa v refhi v reflo vrb vrt out[9:0] start eoc adc clk adc macro v cca figure 11. 'f243/'f241 pseudo dual analog-to-digital converter (adc) module table 16. addresses of adc registers address offset name description 7032h adctrl1 adc control register 1 7034h adctrl2 adc control register 2 7036h adcfifo1 adc 2-level-deep data register fifo for pseudo adc #1 7038h adcfifo2 adc 2-level-deep data register fifo for pseudo adc #2
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 52 post office box 1443 ? houston, texas 772511443 shadowed bits many of the control register bits are described as ashadowedo. this means that changing the value of one of these bits does not take effect until the current conversion is complete. serial peripheral interface (spi) module the 'f243/'f241 devices include the four-pin serial peripheral interface (spi) module. the spi is a high-speed synchronous serial i/o port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multidevice communications are supported by the master/slave operation of the spi. the spi module features include the following: four external pins: spisomi: spi slave-output/master-input pin spisimo: spi slave-input/master-output pin spiste: spi slave transmit-enable pin spiclk: spi serial-clock pin note: all these four pins can be used as gpio, if the spi module is not used. two operational modes: master and slave baud rate: 125 different programmable rates / 5 mbps at 20-mhz cpuclk data word length: one to sixteen data bits four clocking schemes controlled by clock polarity and clock phase bits include: falling edge without phase delay: spiclk active high. spi transmits data on the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. falling edge with phase delay: spiclk active high. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the falling edge of the spiclk signal. rising edge without phase delay: spiclk inactive low. spi transmits data on the rising edge of the spiclk signal and receives data on the falling edge of the spiclk signal. rising edge with phase delay: spiclk inactive low. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. simultaneous receive and transmit operation (transmit function can be disabled in software) transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. eleven spi module control registers: located in control register frame beginning at address 7040h. note: all registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. when a register is acce ssed, the register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. writing to the upper byte has no effect. figure 12 is a block diagram of the spi in slave mode.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 53 post office box 1443 ? houston, texas 772511443 serial peripheral interface (spi) module (continued) s s clock polarity talk cpuclk 4 5 6 0 1 2 spi bit rate state control spirxbuf buffer register 16 clock phase 1 2 30 receiver overrun spictl.4 overrun int ena spiccr.3 0 spibrr.6 0 spiccr.6 spictl.3 spirxbuf.15 0 spidat.15 0 spictl.1 m s m master/slave spi int flag spictl.0 spi int ena spists.7 spidat data register spists.6 m s spictl.2 spi char external connections spisimo spisomi spiste 2 spiclk sw2 s m m s sw3 to cpu m sw1 spipri.6 spi priority level 1 int 1 0 level 6 int spitxbuf.15 0 3 16 spitxbuf buffer register note a: the diagram is shown in the slave mode. 2 the spiste pin is shown as being disabled, meaning that data cannot be transmitted in this mode. note that sw1, sw2, and sw3 ar e closed in this configuration. figure 12. four-pin serial peripheral interface module block diagram
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 54 post office box 1443 ? houston, texas 772511443 serial communications interface (sci) module the 'f243/'f241 devices include a serial communications interface (sci) module. the sci module supports digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the sci receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. to ensure data integrity, the sci checks received data for break detection, parity, overrun, and framing errors. the bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. features of the sci module include: two external pins scitxd: sci transmit-output pin scirxd: sci receive-input pin note: both pins can be used as gpio if not used for sci. baud rate programmable to 64k different rates up to 1250 kbps at 20-mhz cpuclk data word format one start bit data word length programmable from one to eight bits optional even/odd/no parity bit one or two stop bits four error-detection flags: parity, overrun, framing, and break detection two wake-up multiprocessor modes: idle-line and address bit half- or full-duplex operation double-buffered receive and transmit functions transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. transmitter: txrdy flag (transmitter-buffer register is ready to receive another character) and tx empty flag (transmitter-shift register is empty) receiver: rxrdy flag (receiver-buffer register is ready to receive another character), brkdt flag (break condition occurred), and rx error (monitoring four interrupt conditions) separate enable bits for transmitter and receiver interrupts (except brkdt) nrz (non-return-to-zero) format ten sci module control registers located in the control register frame beginning at address 7050h note: all registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. when a register is acces sed, the register data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. writing to the upper byte has no effect. figure 13 shows the sci module block diagram.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 55 post office box 1443 ? houston, texas 772511443 serial communications interface (sci) module (continued) sysclk wut frame format and mode even/odd enable parity sci rx interrupt brkdt scictl1.1 rxrdy scirxst.6 scictl1.3 external connections 8 scictl2.1 rx/bk int ena scirxd scirxst.1 txena sci tx interrupt tx empty txrdy scictl2.0 tx int ena scitxd rxena scirxd clock scictl1.4 rxwake scictl1.0 scictl1.6 rx err int ena txwake scitxd txint sciccr.6 sciccr.5 scitxbuf.70 scihbaud. 15 8 baud rate msbyte register scilbaud. 7 0 scirxbuf.70 receiver-data buffer register scirxst.7 pe fe oe rx error rx error scirxst.4 2 transmitter-data buffer register 8 scictl2.6 scictl2.7 baud rate lsbyte register rxshf register txshf register scirxst.5 rxint 1 scipri.5 scipri.6 sci priority level level 2 int. level 1 int. level 2 int. level 1 int. 1 0 1 0 sci tx priority sci rx priority figure 13. serial communications interface (sci) module block diagram
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 56 post office box 1443 ? houston, texas 772511443 controller area network (can) module the can module is a 16-bit peripheral. the accesses are split into the control/status registers and accesses to the mailbox ram. can peripheral registers: the cpu can access the can peripheral registers only using 16-bit write accesses. the can peripheral always presents full 16-bit data to the cpu bus during read cycles. the can module is a full-can controller designed as a 16-bit peripheral module and supports the following features: can specification 2.0b (active) standard data and remote frames extended data and remote frames six mailboxes for objects of 0- to 8-byte data length two receive mailboxes, two transmit mailboxes two configurable transmit/receive mailboxes local acceptance mask registers for mailboxes 0 and 1 and mailboxes 2 and 3 configurable standard or extended message identifier programmable global mask for objects 1 and 2 and one for object 3 and 4 configurable standard or extended message identifier programmable bit rate programmable interrupt scheme readable error counters self-test mode in this mode, the can module operates in a loop-back fashion, receiving its own transmitted message. can memory map table 17 and table 18 show the register and mailbox locations in the can module.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 57 post office box 1443 ? houston, texas 772511443 can memory map (continued) table 17. register addresses 2 address offset name description 00h mder mailbox direction/enable register (bits 7 to 0) 01h tcr transmission control register (bits 15 to 0) 02h rcr receive control register (bits 15 to 0) 03h mcr master control register (bits 13 to 6, 1, 0) 04h bcr2 bit configuration register 2 (bits 7 to 0) 05h bcr1 bit configuration register 1 (bits 10 to 0) 06h esr error status register (bits 8 to 0) 07h gsr global status register (bits 5 to 0) 08h cec transmit and receive error counters (bits 15 to 0) 09h can_ifr interrupt flag register (bits 13 to 8, 6 to 0) 0ah can_imr interrupt mask register (bits 15, 13 to 0) 0bh lam0_h local acceptance mask mailbox 0 and 1 (bits 31, 28 to 16) 0ch lam0_l local acceptance mask mailbox 0 and 1 (bits 15 to 0) 0dh lam1_h local acceptance mask mailbox 2 and 3 (bits 31, 28 to 16) 0eh lam1_l local acceptance mask mailbox 2 and 3 (bits 15 to 0) 0fh reserved accesses assert the caaddrx signal from the can peripheral (which asserts an illegal address error) 2 all unimplemented register bits are read as zero, writes have no effect. register bits are initialized to zero, unless otherwis e stated in the definition. the mailboxes are situated in one 24 x 32 ram with 16-bit access. it can be written to or read by the cpu or the can. the can write or read access, as well as the cpu read access, needs one clock cycle. the cpu write access needs two clock cycles. in these two clock cycles, the can performs a read-modify-write cycle and, therefore, inserts one wait state for the cpu. address bit 0 of the address bus used when accessing the ram decides if the lower (0) or the higher (1) 16-bit word of the 32-bit word is taken. the ram location is determined by the upper bits 5 to 1 of the address bus. the enable signals for the ram (ez and gz) are always active low. table 18 shows the mailbox locations in ram. one half-word has 16 bits.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 58 post office box 1443 ? houston, texas 772511443 can memory map (continued) table 18. mailbox addresses 2 address offset [5:0] name description upper half-word address bit 0 = 1 description lower half-word address bit 0 = 0 00h msgid0 message id for mailbox 0 message id for mailbox 0 02h msgctrl0 unused rtr and dlc (bits 4 to 0) 04h datalow0 databyte 0, databyte 1 (dbo = 1) databyte 2, databyte 3 (dbo = 1) 04h datalo w 0 databyte 3, databyte 2 (dbo = 0) databyte 1, databyte 0 (dbo = 0) 06h datahigh0 databyte 4, databyte 5 (dbo = 1) databyte 6, databyte 7 (dbo = 1) 06h datahigh0 databyte 7, databyte 6 (dbo = 0) databyte 5, databyte 4 (dbo = 0) 08h msgid1 message id for mailbox 1 message id for mailbox 1 0ah msgctrl1 unused rtr and dlc (bits 4 to 0) 0ch datalow1 databyte 0, databyte 1 (dbo = 1) databyte 2, databyte 3 (dbo = 1) 0ch datalo w 1 databyte 3, databyte 2 (dbo = 0) databyte 1, databyte 0 (dbo = 0) 0eh datahigh1 databyte 4, databyte 5 (dbo = 1) databyte 6, databyte 7 (dbo = 1) ... ... ... ... 28h msgid5 message id for mailbox 5 message id for mailbox 5 2ah msgctrl5 unused rtr and dlc (bits 4 to 0) 2ch datalow5 databyte 0, databyte 1 (dbo = 1) databyte 2, databyte 3 (dbo = 1) 2ch datalo w 5 databyte 3, databyte 2 (dbo = 0) databyte 3, databyte 2 (dbo = 0) 2eh datahigh5 databyte 4, databyte 5 (dbo = 1) databyte 6, databyte 7 (dbo = 1) 2eh datahigh5 databyte 7, databyte 6 (dbo = 0) databyte 5, databyte 4 (dbo = 0) 2 the dbo (data byte order) bit is located in the mcr register and is used to define the order in which the data bytes are stored in the mailbox when received and the order in which the data bytes are transmitted. byte 0 is the first byte in the message and byte 7 is the last one as shown in the can message. can interrupt logic there are two interrupt requests from the can module to the peripheral interrupt expansion (pie) controller: the mailbox interrupt and the error interrupt. both interrupts can assert either a high-priority request or a low-priority request to the cpu. the following events can initiate an interrupt: transmission interrupt a message was transmitted or received successfully e asserts the mailbox interrupt. abort acknowledge interrupt a send transmission was aborted e asserts the error interrupt. write denied interrupt the cpu tried to write to a mailbox but was not allowed to e asserts the error interrupt. wakeup interrupt after wakeup, this interrupt is generated e asserts the error interrupt, even when clocks are not running. receive message lost interrupt an old message was overwritten by a new one e asserts the error interrupt. bus-off interrupt the can module enters the bus-off state e asserts the error interrupt. error passive interrupt the can module enters the error passive mode e asserts the error interrupt. warning level interrupt one or both of the error counters is greater than or equal to 96 e asserts the error interrupt.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 59 post office box 1443 ? houston, texas 772511443 can configuration mode normal mode (ccr = 0) (cce = 0) configuration mode requested (ccr = 1) (cce = 0) wait for configuration mode (ccr = 1) (cce = 0) configuration mode active (ccr = 1) (cce = 1) changing of bit timing parameters enabled normal mode requested (ccr = 0) (cce = 1) wait for normal mode (ccr = 0) (cce = 1) cce = 1 cce = 0 figure 14. can initialization
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 60 post office box 1443 ? houston, texas 772511443 can configuration mode (continued) the can module must be initialized before activation. this is only possible if the module is in configuration mode. the configuration mode is set by programming the ccr bit of the mcr register with a1o. only if the status bit cce (gsr.4) confirms the request by getting a1o, the initialization can be performed. afterwards, the bit configuration registers can be written. the module is activated again by programming the control bit ccr with zero. after a hardware reset, the configuration mode is active. can power-down mode (pdm) the can peripheral's own low-power mode must be requested before a device low-power mode is entered by executing the idle instruction, if the device low-power mode is going to shut off the peripheral clocks. before the cpu enters its idle mode to enter the device low-power mode to potentially shut off all device clocks, it must first request a can peripheral power-down by writing a a1o to the pdr bit in mcr. if the module is transmitting a message when pdr is set, the transmission is continued until a successful transmission, a lost arbitration, or an error condition on the can bus line occurs. then, the pda is asserted. therefore, the module causes no error condition on the can bus line. when the module is ready to enter power-down mode, the status bit pda is set. the cpu must then poll the pda bit in gsr, and only enter idle after pda is set. on exiting the power-down mode, the pdr flag in the mcr must be cleared by software or is cleared automatically if the wuba bit in mcr is set and if there is any bus activity on the can bus line. when detecting a dominant signal on the can bus, the wakeup interrupt flag wuif (can_ifr.3) is asserted. the power-down mode is exited as soon as the clock is switched on. there is no internal filtering for the can bus line. the automatic wakeup on bus activity can be enabled or disabled by setting the configuration bit wuba (mcr.9). if there is any activity on the can bus line, the module begins its power up sequence. the module waits until detecting 11 consecutive recessive bits on the canrx pin and goes to bus active afterwards. the first message, which initiates the bus activity, cannot be received. when wuba is enabled, the error interrupt wuif is asserted automatically to the pie controller, which handles it as a wakeup interrupt and restart the device clocks if they are stopped. after leaving the sleep mode with a wakeup, the pdr and pda bits (mcr.11 and gsr.3, respectively) are cleared. the can error counters remain unchanged. watchdog (wd) timer module the 'f243/'f241 devices include a watchdog (wd) timer module. the wd function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. the wd timer operates independently of the cpu and is always enabled. it does not need any cpu initialization to function. when a system reset occurs, the wd timer defaults to the fastest wd timer rate available (6.55 ms for a 39 062.5-hz wdclk signal). as soon as reset is released internally, the cpu starts executing code, and the wd timer begins incrementing. this means that, to avoid a premature reset, wd setup should occur early in the power-up sequence. see figure 15 for a block diagram of the wd module. the wd module features include the following: wd timer seven different wd overflow rates ranging from 6.55 ms to 1 s a wd-reset key (wdkey) register that clears the wd counter when a correct value is written, and generates a system reset if an incorrect value is written to the register wd check bits that initiate a system reset if an incorrect value is written to the wd control register (wdcr) automatic activation of the wd timer, once system reset is released three wd control registers located in control register frame beginning at address 7020h. note: all registers in this module are 8-bit registers. when a register is accessed, the register data is in the lower byte, the upper byte is read as zeros. writing to the upper byte has no effect. figure 15 shows the wd block diagram. table 19 shows the different wd overflow (timeout) selections.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 61 post office box 1443 ? houston, texas 772511443 watchdog (wd) timer module (continued) 55 + aa detector system reset request wdcntr.7 0 6-bit free- running counter /64 /32 /16 /8 /4 /2 111 110 101 100 011 010 001 000 wdclk system reset system reset clr one-cycle delay watchdog reset key register 8-bit watchdog counter clr bad wdcr key good key bad key wdps wdcr.2 0 210 wdkey.7 0 wdchk20 wdcr.5 3 2 wdcr.7 wdflag reset flag ps/257 wddis wdcr.6 101 (constant value) 3 3 2 writing to bits wdcr.5 3 with anything but the correct pattern (101) generates a system reset. figure 15. block diagram of the wd module
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 62 post office box 1443 ? houston, texas 772511443 watchdog (wd) timer module (continued) table 19. wd overflow (timeout) selections wd prescale select bits 39.0625-khz wdclk 2 wdps2 wdps1 wdps0 wdclk divider frequency (hz) minimum overflow (ms) 0 0 x 3 1 152.59 6.55 0 1 0 2 76.29 13.11 0 1 1 4 38.15 26.21 1 0 0 8 19.07 52.43 1 0 1 16 9.54 104.86 1 1 0 32 4.77 209.72 1 1 1 64 2.38 419.43 2 generated by 5-mhz clock 3 x = don't care scan-based emulation tms320x2xx devices incorporate scan-based emulation logic for code-development and hardware-development support. scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. the scan-based emulator communicates with the 'x2xx by way of the ieee 1149.1-compatible (jtag) interface. the 'f243 and 'f241 dsps, like the tms320f206, tms320c203, and tms320lc203, do not include boundary scan. the scan chain of these devices is useful for emulation function only. tms320x24x instruction set the 'x24x microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. source code for the 'c1x and 'c2x dsps is upwardly compatible with the 'x243/'x241 devices. for maximum throughput, the next instruction is prefetched while the current one is being executed. because the same data lines are used to communicate to external data, program, or i/o space, the number of cycles an instruction requires to execute varies, depending upon whether the next data operand fetch is from internal or external memory. highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes the tms320x24x instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. in direct addressing, the instruction word contains the lower seven bits of the data memory address. this field is concatenated with the nine bits of the data memory page pointer (dp) to form the 16-bit data memory address. therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, each page containing 128 words. indirect addressing accesses data memory through the auxiliary registers. in this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. eight auxiliary registers (ar0 ar7) provide flexible and powerful indirect addressing. to select a specific auxiliary register, the auxiliary register pointer (arp) is loaded with a value from 0 to 7 for ar0 through ar7, respectively.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 63 post office box 1443 ? houston, texas 772511443 addressing modes (continued) there are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or subtracting the contents of ar0, single-indirect addressing with no increment or decrement, and bit-reversed addressing [used in fast fourier transforms (ffts)] with increment or decrement. all operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and arp can be modified. in immediate addressing, the actual operand data is provided in a portion of the instruction word or words. there are two types of immediate addressing: long and short. in short-immediate addressing, the data is contained in a portion of the bits in a single-word instruction. in long-immediate addressing, the data is contained in the second word of a two-word instruction. the immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution (for example, initialization values or constants). the register-addressing mode uses operands in cpu registers either explicitly, such as with a direct reference to a specific register, or implicitly, with instructions that intrinsically reference certain registers. in either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. repeat feature the repeat function can be used with instructions (as defined in table 21) such as multiply/accumulates (mac and macd), block moves (bldd and blpd), i/o transfers (in/out ), and table read/writes (tblr/tblw). these instructions, although normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. for example, the table-read instruction can take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. the repeat counter (rptc) is loaded with the addressed data memory location if direct or indirect addressing is used, and with an 8-bit immediate value if short-immediate addressing is used. the internal rptc register is loaded by the rpt instruction. this results in a maximum of n + 1 executions of a given instruction. rptc is cleared by reset. once a repeat instruction (rpt ) is decoded, all interrupts, including nmi (but excluding reset), are masked until the completion of the repeat loop. instruction set summary this section summarizes the operation codes (opcodes) of the instruction set for the 'x24x digital signal processors. this instruction set is a superset of the 'c1x and 'c2x instruction sets. the instructions are arranged according to function and are alphabetized by mnemonic within each category. the symbols in table 20 are used in the instruction set summary table (table 21). t he ti 'c2xx assembler accepts 'c2x instructions. the number of words that an instruction occupies in program memory is specified in column 3 of table 22. several instructions specify two values separated by a slash mark ( / ) for the number of words. in these cases, different forms of the instruction occupy a different number of words. for example, the add instruction occupies one word when the operand is a short-immediate value or two words if the operand is a long-immediate value. the number of cycles that an instruction requires to execute is also in column 3 of table 22. all instructions are assumed to be executed from internal program memory (ram) and internal data dual-access memory. the cycle timings are for single-instruction execution, not for repeat mode.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 64 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 20. tms320x24x opcode symbols symbol description a address acc accumulator accb accumulator buffer arx auxiliary register value (0 7) bitx 4-bit field that specifies which bit to test for the bit instruction bmar block-move address register dbmr dynamic bit-manipulation register i addressing-mode bit ii...ii immediate operand value intm interrupt-mode flag bit intr# interrupt vector number k constant preg product register prog program memory rptc repeat counter shf, shft 3/4-bit shift value tc test-control bit t p two bits used by the conditional execution instructions to represent the conditions tc, ntc, and bio. t p meaning 0 0 bio low 0 1 tc = 1 1 0 tc = 0 1 1 none of the above conditions tregn temporary register n (n = 0, 1, or 2) z l v c 4-bit field representing the following conditions: z: acc = 0 l: acc < 0 v: overflow c: carry a conditional instruction contains two of these 4-bit fields. the 4-lsb field of the instruction is a 4-bit mask field. a 1 in the corresponding mask bit indicates that the condition is being tested. the second 4-bit field (bits 4 7) indicates the state of the conditions designated by the mask bits as being tested. for example, to test for acc 0, the z and l fields are set while the v and c fields are not set. the next 4-bit field contains the state of the conditions to test. the z field is set to indica te testing of the condition acc = 0, and the l field is reset to indicate testing of the condition acc 0. the conditions possible with these 8 bits are shown in the bcnd and cc instructions. to determine if the conditions are met, the 4-lsb bit mask is anded with the conditions. if any bits are set, the conditions are met.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 65 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 21. tms320x24x instruction set summary 'x24x description words/ opcode mnemonic description cycles msb lsb abs absolute value of accumulator 1/1 1011 1110 0000 0000 add to accumulator with shift 1/1 0010 shft iadd ress add add to high accumulator 1/1 0110 0001 iadd ress add add to accumulator short immediate 1/1 1011 1000 kkkk kkkk add to accumulator long immediate with shift 2/2 1011 1111 1001 shft addc add to accumulator with carry 1/1 0110 0000 iadd ress adds add to low accumulator with sign extension suppressed 1/1 0110 0010 iadd ress addt add to accumulator with shift specified by t register 1/1 0110 0011 iadd ress adrk add to auxiliary register short immediate 1/1 0111 1000 kkkk kkkk and with accumulator 1/1 0110 1110 iadd ress and immediate with accumulator with shift 2/2 1011 1111 1011 shft and and immediate with accumulator with shift 2/2 16-bit constant and immediate with accumulator with shift of 16 2/2 1011 1110 1000 0001 and immediate with accumulator with shift of 16 2/2 16-bit constant apac add p register to accumulator 1/1 1011 1110 0000 0100 b branch unconditionally 2/4 0111 1001 iadd ress b branch unconditionally 2/4 branch address bacc branch to address specified by accumulator 1/4 1011 1110 0010 0000 banz branch on auxiliary register not zero 2/4/2 0111 1011 iadd ress banz branch on auxiliary register not zero 2/4/2 branch address branch if tc bit 0 2/4/2 1110 0001 0000 0000 branch if tc bit ??? ?????? ??????? ?????? ?? ?? ?? ??? ??? ? ?????? ?? ?? ?? ??? ?????? ??????? ?????? ?? ???? ??? ??? ?? ? ? ?????? ?? ???? ??? ?????? ??????? ?????? ?? ????????? 0 2/4/2 1110 0011 1000 1100 branch if accumulator ??? ?????? ??????? ?????? ?? ????????? > 0 2/4/2 1110 0011 0000 0100 branch if accumulator > 0 2/4/2 branch address bcnd branch on i/o status low 2/4/3 1110 0000 0000 0000 branch on i/o status low 2/4/3 branch address branch if accumulator 0 2/4/2 1110 0011 1100 1100 branch if accumulator ??? ?????? ??????? ?????? ?? ????????? < 0 2/4/2 1110 0011 0100 0100 branch if acc u m u lator < 0 2/4/2 branch address branch on no carry 2/4/2 1110 0011 0000 0001 branch on no carr y 2/4/2 branch address branch if no overflow 2/4/2 1110 0011 0000 0010 branch if no o v erflo w 2/4/2 branch address
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 66 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 21. tms320x24x instruction set summary (continued) 'x24x description words/ opcode mnemonic description cycles msb lsb branch if accumulator 0 2/4/2 1110 0011 0000 1000 branch if acc u m u lator ??? ?????? ??????? ???? ?????? ?? ???????? ??? ??? ?? ? ? ???? ?????? ?? ? ? ????? ? ??? ?????? ??????? ?????? ?? ????????? ??? ??? ?? ? ? ?????? ?? ??? ????? ??? ?????? ??????? ??? ???? ?? ?? ? ??? ???? ??? ???? ???? ?? ???????? ? ??? ?? ?? ???? ???? ??? 2 ????? ??? ??? ???? ??? ?? ???? ??? ????? ???????? ?? ?? ? ???? ??? ???? 2 ????? ? ? ? ??? ???? ??? ?? ???? ??? ?? ??? ???????? ?? ?????? ??????? ???? 2 ????? ??? ??? ???? ??? ?? ???? ??? ??????????? ???????? ?? ?? ?? ???? ??? ????? ? ? ? ??? ???? ??? ?? ???? ??? ??????????? ???????? ?? ?????? ??????? ??? ????? ??? ??? ????? ??? ?? ???? ??? ?? ?? ?? ???? ??? ??? ????? ? ? ? ??? ????? ??? ?? ???? ??? ?? ?????? ??????? ???? ???? ??????? ???????? ?? ??? ??? ?? ???? ???? ??????? ?? ??? ?? ???? ??? ???? ???? ? ?? ???? ?? ????? ??????? ?? ??????????? ???? ??????? ??? ??? ?? ???? ???? ?? ??????????? ???? ? ?? ???? ??? ????? ??????? ???????? ???? ?? ???? ??? ?? ??? ??? ? ? ????? ??????? ?? ??? ??? ? ???? ???? ?? ?? ??? ??? ? ??? ??? ???? ???????? ??? ?? ??? ??? ? ? ???? ???????????? ??? ?? ??? ??? ? ?? ???? ???? ??????? ???? ?? ??? ??? ? ?? ???? ??????? ???? ?? ??? ??? ? ?? ??? ???????? ????????? ?? ??? ??? ? ??? ?????? ?????? ???????? ???? ?????? ???????? ?? ?? ??? ???? ? ??? ??? ???? ??? ?? ???? ??? ?? ??? ??? ???? ??? ???? ???? ???? ??????? ?? ??? ??? ? ? ?? ?? ? ???? ??? ??? ?? ?? ???? ???? ??? ?? ?? ? ???? ??? ??? ?? ?M??? ?? ?? ??? ??? ??????????????? ?? ??? ??? ??k kkkk ???? ????????? ???? ????? ?? ? ???? ???? ??? ???? ???? ????????? ???? ???????? ???? ????? ?? ??? ???? ? ???? ???? ???? ??? ????? ???? ???????? ? ??? ????? ?? ?M??? ???????? ???? ??? ????????? ??? ???? ???? ????????? ?? ?? ?? ???? ??? 2 ?? ??? ??????? ??? ???? ?????????? ???? ??? ???? ???? ???????? ????????? ??? ??? ??? ???
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 67 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 21. tms320x24x instruction set summary (continued) 'x24x description words/ opcode mnemonic description cycles msb lsb load accumulator immediate short 1/1 1011 1001 kkkk kkkk lacl zero accumulator 1/1 1011 1001 0000 0000 lacl zero low accumulator and load high accumulator 1/1 0110 1010 iadd ress zero low accumulator and load low accumulator with no sign extension 1/1 0110 1001 iadd ress lact load accumulator with shift specified by t register 1/1 0110 1011 iadd ress load auxiliary register 1/2 0000 0arx iadd ress lar load auxiliary register short immediate 1/2 1011 0arx kkkk kkkk lar load auxiliary register long immediate 2/2 1011 1111 0000 1arx load a ux iliar y register long immediate 2/2 16-bit constant ldp load data-memory page pointer 1/2 0000 1101 iadd ress ldp load data-memory page pointer immediate 1/2 1011 110p agep oint lph load high-p register 1/1 0111 0101 iadd ress lst load status register st0 1/2 0000 1110 iadd ress lst load status register st1 1/2 0000 1111 iadd ress lt load treg 1/1 0111 0011 iadd ress lta load treg and accumulate previous product 1/1 0111 0000 iadd ress ltd load treg, accumulate previous product, and move data 1/1 0111 0010 iadd ress ltp load treg and store p register in accumulator 1/1 0111 0001 iadd ress lts load treg and subtract previous product 1/1 0111 0100 iadd ress mac multi p ly and accumulate 2/3 1010 0010 iadd ress mac m u ltipl y and acc u m u late 2/3 16-bit constant macd multi p ly and accumulate with data move 2/3 1010 0011 iadd ress macd m u ltipl y and acc u m u late w ith data mo v e 2/3 16-bit constant mar load auxiliary register pointer 1/1 1000 1011 1000 1arx mar modify auxiliary register 1/1 1000 1011 iadd ress mpy multiply (with treg, store product in p register) 1/1 0101 0100 iadd ress mpy multiply immediate 1/1 110c kkkk kkkk kkkk mpya multiply and accumulate previous product 1/1 0101 0000 iadd ress mpys multiply and subtract previous product 1/1 0101 0001 iadd ress mpyu multiply unsigned 1/1 0101 0101 iadd ress neg negate accumulator 1/1 1011 1110 0000 0010 nmi nonmaskable interrupt 1/4 1011 1110 0101 0010 nop no operation 1/1 1000 1011 0000 0000 norm normalize contents of accumulator 1/1 1010 0000 iadd ress or with accumulator 1/1 0110 1101 iadd ress or immediate with accumulator with shift 2/2 1011 1111 1100 shft or or immediate w ith acc u m u lator w ith shift 2/2 16-bit constant or immediate with accumulator with shift of 16 2/2 1011 1110 1000 0010 or immediate w ith acc u m u lator w ith shift of 16 2/2 16-bit constant out output data to port 2/3 0000 16bit 1100 i/o iadd port ress adrs pac load accumulator with p register 1/1 1011 1110 0000 0011
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 68 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 21. tms320x24x instruction set summary (continued) 'x24x description words/ opcode mnemonic description cycles msb lsb pop pop top of stack to low accumulator 1/1 1011 1110 0011 0010 popd pop top of stack to data memory 1/1 1000 1010 iadd ress pshd push data-memory value onto stack 1/1 0111 0110 iadd ress push push low accumulator onto stack 1/1 1011 1110 0011 1100 ret return from subroutine 1/4 1110 1111 0000 0000 retc conditional return from subroutine 1/4/2 1110 11tp zlvc zlvc rol rotate accumulator left 1/1 1011 1110 0000 1100 ror rotate accumulator right 1/1 1011 1110 0000 1101 rpt repeat instruction as specified by data-memory value 1/1 0000 1011 iadd ress rpt repeat instruction as specified by immediate value 1/1 1011 1011 kkkk kkkk sach store high accumulator with shift 1/1 1001 1shf iadd ress sacl store low accumulator with shift 1/1 1001 0shf iadd ress sar store auxiliary register 1/1 1000 0arx iadd ress sbrk subtract from auxiliary register short immediate 1/1 0111 1100 kkkk kkkk set carry bit 1/1 1011 1110 0100 1111 configure block as program memory 1/1 1011 1110 0100 0101 disable interrupt 1/1 1011 1110 0100 0001 setc set overflow mode 1/1 1011 1110 0100 0011 set test / control flag 1/1 1011 1110 0100 1011 set external flag xf 1/1 1011 1110 0100 1101 set sign-extension mode 1/1 1011 1110 0100 0111 sfl shift accumulator left 1/1 1011 1110 0000 1001 sfr shift accumulator right 1/1 1011 1110 0000 1010 spac subtract p register from accumulator 1/1 1011 1110 0000 0101 sph store high-p register 1/1 1000 1101 iadd ress spl store low-p register 1/1 1000 1100 iadd ress spm set p register output shift mode 1/1 1011 1111 iadd ress sqra square and accumulate 1/1 0101 0010 iadd ress sqrs square and subtract previous product from accumulator 1/1 0101 0011 iadd ress sst store status register st0 1/1 1000 1110 iadd ress sst store status register st1 1/1 1000 1111 iadd ress splk store long immediate to data memory 2/2 1010 1110 iadd ress splk store long immediate to data memor y 2/2 16-bit constant subtract from accumulator long immediate with shift 2/2 1011 1111 1010 shft s u btract from acc u m u lator long immediate w ith shift 2/2 16-bit constant sub subtract from accumulator with shift 1/1 0011 shft iadd ress subtract from high accumulator 1/1 0110 0101 iadd ress subtract from accumulator short immediate 1/1 1011 1010 kkkk kkkk
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 69 post office box 1443 ? houston, texas 772511443 instruction set summary (continued) table 21. tms320x24x instruction set summary (continued) 'x24x description words/ opcode mnemonic description cycles msb lsb subb subtract from accumulator with borrow 1/1 0110 0100 iadd ress subc conditional subtract 1/1 0000 1010 iadd ress subs subtract from low accumulator with sign extension suppressed 1/1 0110 0110 iadd ress subt subtract from accumulator with shift specified by treg 1/1 0110 0111 iadd ress tblr table read 1/3 1010 0110 iadd ress tblw table write 1/3 1010 0111 iadd ress trap software interrupt 1/4 1011 1110 0101 0001 exclusive-or with accumulator 1/1 0110 1100 iadd ress exclusive or immediate with accumulator with shift 2/2 1011 1111 1101 shft xor e x cl u si v e - or immediate w ith acc u m u lator w ith shift 2/2 16-bit constant exclusive or immediate with accumulator with shift of 16 2/2 1011 1110 1000 0011 e x cl u si v e - or immediate w ith acc u m u lator w ith shift of 16 2/2 16-bit constant zalr zero low accumulator and load high accumulator with rounding 1/1 0110 1000 iadd ress development support texas instruments offers an extensive line of development tools for the 'x24x generation of dsps, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of 'x24x-based applications: software development tools: assembler/linker simulator optimizing ansi c compiler application algorithms c/assembly debugger and code profiler hardware development tools: emulator xds510 (supports 'x24x multiprocessor system debug) the tms320 dsp development support reference guide (literature number spru011) contains information about development support products for all tms320 family member devices, including documentation. refer to this document for further information about tms320 documentation or any other tms320 support products from texas instruments. there is also an additional document, the tms320 third-party support reference guide (literature number spru052), which contains information about tms320-related products from other companies in the industry. to receive copies of tms320 literature, contact the literature response center at 800/477-8924. see table 22 and table 23 for complete listings of development support tools for the 'x24x. for information on pricing and availability, contact the nearest ti field sales office or authorized distributor.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 70 post office box 1443 ? houston, texas 772511443 development support (continued) table 22. development support tools development tool platform part number software compiler/assembler/linker sparc ? tmds3242555-08 compiler/assembler/linker pc-dos ? tmds3242855-02 assembler/linker pc-dos, os/2 ? tmds3242850-02 'c2xx simulator pc-dos, win ? tmdx324x851-02 'c2xx simulator sparc tmdx324x551-09 digital filter design package pc-dos dfdp 'c2xx debugger/emulation software pc-dos, os/2, win tmdx324012xx 'c2xx debugger/emulation software sparc tmdx324062xx hardware xds510xl ? emulator pc-dos, os/2 tmds00510 xds510ws ? emulator sparc tmds00510ws table 23. tms320x24x-specific development tools development tool platform part number hardware 'f240 evm pc tmdx326p124x device and development support tool nomenclature to designate the stages in the product development cycle, texas instruments assigns prefixes to the part numbers of all tms320 devices and support tools. each tms320 member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx / tmdx) through fully qualified production devices/tools (tms / tmds). this development flow is defined below. device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification tms fully-qualified production device sparc is a trademark of sparc international, inc. pc-dos and os/2 are trademarks of international business machines corp. win is a trademark of microsoft corp. xds510xl and xds510ws are trademarks of texas instruments incorporated.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 71 post office box 1443 ? houston, texas 772511443 device and development support tool nomenclature (continued) support tool development evolutionary flow: tmdx development support product that has not completed ti's internal qualification testing tmds fully qualified development support product tmx and tmp devices and tmdx development support tools are shipped against the following disclaimer: adevelopmental product is intended for internal evaluation purposes.o tms devices and tmds development support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. ti's standard warranty applies. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pn, pq, and pz) and temperature range (for example, l). figure 16 provides a legend for reading the complete device name for any tms320x2xx family member. prefix temperature range (default: 0 c to 70 c) tms 320 f 243 pge (l) tmx = experimental device tmp = prototype device tms = qualified device device family 320 = tms320 family technology l=0 c to 70 c a=40 c to 85 c s=40 c to 125 c q= 40 c to 125 c, q 100 fault grading package type 2 fn = 68-pin plcc pg = 64-pin plastic qfp pge = 144-pin plastic qfp c = cmos e = cmos eprom f = flash eeprom lc = low-voltage cmos (3.3 v) vc = low-voltage cmos (3 v) device '20x dsp 203 206 209 '24x dsp 240 241 242 243 (b) boot-loader option 2 plcc = plastic j-leaded chip carrier qfp = quad flatpack figure 16. tms320 device nomenclature
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 72 post office box 1443 ? houston, texas 772511443 documentation support extensive documentation supports all of the tms320 family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user's guides for all devices and development support tools; and hardware and software applications. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 newsletter, details on signal processing , is published quarterly and distributed to update tms320 customers on product information. updated information on the tms320 dsp controllers can be found on the worldwide web at: http://www.ti.com/dsps . to send comments regarding the 'f243/'f241 datasheet (sprs064a), use the comments@books.sc.ti.com email address, which is a repository for feedback. for questions and support, contact the product information center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 73 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v dd 3 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : l version('f243/'f241) 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . a version('f243/'f241) 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . s version('f241) 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 all voltage values are with respect to v ss .
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 74 post office box 1443 ? houston, texas 772511443 recommended operating conditions min nom max unit v dd supply voltage 4.5 5 5.5 v v ss supply ground 0 v xtal1/clkin 3 v dd +03 v ih high - level in p ut voltage xtal1/clkin 3 v dd + 0 . 3 v v ih high-level in ut voltage all other inputs 2 v dd + 0.3 v xtal1/clkin 03 07 v il low - level in p ut voltage xtal1/clkin 0 . 3 0 . 7 v v il low-level in ut voltage all other inputs 0.3 0.7 v i oh high - level out p ut current v oh =24v all out p uts 8 ma i oh high-level out ut current , v oh = 2 . 4 v all out uts 8 ma i ol low - level out p ut current v ol =07v all out p uts 8 ma i ol low-level out ut current , v ol = 0 . 7 v all out uts 8 ma l version 0 70 t a operating free-air temperature a version 40 85 c s version 40 125 t fp flash programming on flash devices, temperature 40 85 c thermal resistance values, q ja (junction-to-ambient) and q jc (junction-to-case) for the 'f243/'f241 can be found on the mechanical package pages. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage 5-v operation, i oh = max = 8 ma 2.4 v v ol low-level output voltage 5-v operation, i ol = max = 8 ma 0.7 v trst pins with internal pulldown 350 i i input current (v i = v ss or v dd ) emu0, emu1, tms, tck, and tdi with internal pullup 3 50 65 m a all other input-only pins 5 5 i oz output current, high-impedance state (off-state) v o = v dd or 0 v 5 5 m a su pp ly current o p erating mode 5vo p eration t (co) =50ns '243 120 ma s u ppl y c u rrent , operating mode 5 - v operation , t c(co) = 50 ns '241 90 ma i dd supply current, idle 1 low-power mode lpm0 5-v operation, t c(co) = 50 ns 40 ma i dd supply current, idle 2 low-power mode lpm1 5-v operation, t c(co) = 50 ns 30 ma supply current, pll/osc power-down mode lpm2 5-v operation, at room temperature 10 m a c i input capacitance 15 pf c o output capacitance 15 pf
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 75 post office box 1443 ? houston, texas 772511443 parameter measurement information tester pin electronics v load i ol c t i oh output under test 50 w where: i ol = 2 ma (all outputs) i oh = 300 m a (all outputs) v load = 1.5 v c t = 110-pf typical load-circuit capacitance figure 17. test load circuit signal transition levels the data in this section is shown for the 5-v version. note that some of the signals use different reference voltages, see the recommended operating conditions table. ttl-output levels are driven to a minimum logic-high level of 2.4 v and to a maximum logic-low level of 0.7 v. figure 18 shows the ttl-level outputs. 0.7 v (v ol ) 20% 2.4 v (v oh ) 80% figure 18. ttl-level outputs ttl-output transition times are specified as follows: for a high-to-low transition , the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower. for a low-to-high transition , the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher. figure 19 shows the ttl-level inputs. 0.7 v (v il ) 10% 2.0 v (v ih ) 90% figure 19. ttl-level inputs ttl-compatible input transition times are specified as follows: for a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower. for a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 76 post office box 1443 ? houston, texas 772511443 parameter measurement information timing parameter symbology timing parameter symbols used are created in accordance with jedec standard 100-a. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: a a[15:0] ms memory strobe pins is , ds , or ps cl xtal1/clkin r ready co clkout rd read cycle or rd d d[15:0] rs reset pin rs int nmi , xint1, xint2 w write cycle or we lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid f fall time x unknown, changing, or don't care level h hold time z high impedance r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing parameters all output signals from the 'f243/'f241 devices (including clkout) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. the signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. for actual cycle examples, refer to the appropriate cycle description section of this data sheet.
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 77 post office box 1443 ? houston, texas 772511443 clock characteristics and timings clock options parameter pll multiply-by-4 the 'f243/'f241 devices include an on-chip pll which is hardwired for multiply-by-4 operation. this requires the use of a 5-mhz clock input frequency for 20-mhz device operation. this input clock can be provided from either an external reference crystal or oscillator. external reference crystal clock option the internal oscillator is enabled by connecting a crystal across xtal1/clkin and xtal2 pins as shown in figure 20a. the crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 w and a power dissipation of 1 mw; it should be specified at a load capacitance of 20 pf. external reference oscillator clock option the internal oscillator is disabled by connecting a ttl-level clock signal to xtal1/clkin and leaving the xtal2 input pin unconnected as shown in figure 20b. external clock signal (toggling 0 5 v) c2 (see note a) c1 (see note a) crystal xtal2 xtal1/clkin xtal1/clkin xtal2 nc note a: for the values of c1 and c2, see the crystal manufacturer's specification. (a) (b) figure 20. recommended crystal / clock connection
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 78 post office box 1443 ? houston, texas 772511443 external reference crystal/clock with pll circuit enabled the internal oscillator is enabled by connecting a crystal across xtal1/clkin and xtal2 pins as shown in figure 20a. the crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 and a power dissipation of 1 mw; it should be specified at a load capacitance of 20 pf. timings with the pll circuit enabled parameter min typ max unit f input clock frequency oscillator 1 5 mhz f x i npu t c l oc k f requency clkin 1 5 mhz c1, c2 load capacitance 10 pf switching characteristics over recommended operating conditions [h = 0.5 t c(co) ] (see figure 21) parameter clock mode min typ max unit t c(co) cycle time, clkout 50 ns t f(co) fall time, clkout 4 ns t r(co) rise time, clkout 4 ns t w(col) pulse duration, clkout low h3 h h+3 ns t w(coh) pulse duration, clkout high h3 h h+3 ns t p transition time, pll synchronized after pll enabled before pll lock, clkin multiply by 4 2500t c(cl) ns timing requirements (see figure 21) external reference crystal min max unit t c(cl) cycle time, xtal1/clkin 5 mhz 200 ns t f(cl) fall time, xtal1/clkin 5 ns t r(cl) rise time, xtal1/clkin 5 ns t w(cil) pulse duration, xtal1/clkin low as a percentage of t c(cl) 40 60 % t w(cih) pulse duration, xtal1/clkin high as a percentage of t c(cl) 40 60 % xtal1/clkin clkout t c(ci) t w(cil) t w(cih) t w(col) t w(coh) t c(co) t f(cl) t r(cl) t r(co) t f(co) figure 21. clkin-to-clkout timing for pll oscillator mode, multiply-by-4 option with 5-mhz clock
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 79 post office box 1443 ? houston, texas 772511443 low-power mode timings switching characteristics over recommended operating conditions [h = 0.5t c(co) ] (see figure 22, figure 23, and figure 24) parameter low-power modes min typ max unit t d(wake a) dela y time, clkout switchin g to idle1 lpm0 4+6t (co) 15 t (co) ns t d(wake-a) y, g program execution resume idle1 lpm0 4 + 6 t c(co) 15 t c(co) ns t d(idle-coh) delay time, idle instruction executed to clkout high idle2 lpm1 4t c(co) ns t d(wake-osc) delay time, wakeup interrupt asserted to oscillator running halt {pll/osc p ower down} lpm2 osc start-up and pll lock time ms t d(idle-osc) delay time, idle instruction executed to oscillator power off {pll/osc power d own } lpm2 4t c(co) m s t d(ex) delay time, reset vector executed after rs high 36h ns wake int clkout a0a15 t d(wakea) figure 22. idle1 entry and exit timing lpm0 t d(wakea) t d(idlecoh) wake int clkout a0a15 figure 23. idle2 entry and exit timing lpm1 t d(ex) t d(idlecoh) t d(idleosc) reset clkout a0a15 t d(wakeosc) figure 24. halt mode lpm2 note: wake int can be any valid interrupt or reset
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 80 post office box 1443 ? houston, texas 772511443 rs timings switching characteristics over recommended operating conditions for a reset [h = 0.5t c(co) ] (see figure 25) parameter min max unit t w(rsl1) pulse duration, rs low 2 8t c(co) ns t d(ex) delay time, reset vector executed after rs high 36h ns 2 the parameter t w(rsl1) refers to the time rs is an output. a0a15 clkout rs xtal1/ clkin t w(rsl1) t d(ex) figure 25. watchdog reset pulse timing requirements for a reset [h = 0.5t c(co) ] (see figure 26) min max unit t w(rsl) pulse duration, rs low 3 5 ns t d(ex) delay time, reset vector executed after rs high 36h ns 3 the parameter t w(rsl) refers to the time rs is an input rs xtal1/ clkin a0a15 clkout case a. power-on reset t w(rsl) + x t d(ex) rs xtal1/ clkin clkout a0a15 case b. external reset after power-on t w(rsl) + x t d(ex) the value of x depends on the reset condition as follows: pll enabled: assuming clkin is stable, x=pll lock-up time. if the internal oscillator is used, x=oscillator lock-up time + pll lock-up time. in case of resets after power on reset, x=0 (i.e., t w(rsl) =8h ns only). figure 26. reset timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 81 post office box 1443 ? houston, texas 772511443 xf, bio , and mp/mc timings switching characteristics over recommended operating conditions (see figure 27) parameter min max unit t d(xf) delay time, clkout high to xf high/low 3 7 ns timing requirements (see figure 27) min max unit t su(bio)co setup time, bio or mp/mc low before clkout low 0 ns t h(bio)co hold time, bio or mp/mc low after clkout low 19 ns t d(xf) xf bio , mp/mc clkout t su(bio)co t h(bio)co figure 27. xf and bio timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 82 post office box 1443 ? houston, texas 772511443 timing event manager interface pwm timings pwm refers to pwm outputs on pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, t1pwm, and t2pwm. switching characteristics over recommended operating conditions for pwm timing [h = 0.5t c(co) ] (see figure 28) parameter min max unit t w(pwm) 2 pulse duration, pwm output high/low 2h+5 ns t d(pwm)co delay time, clkout low to pwm output switching 15 ns 2 pwm outputs may be 100%, 0%, or increments of t c(co) with respect to the pwm period. timing requirements 3 [h = 0.5t c(co) ] (see figure 29) min max unit t w(tmrdir) pulse duration, tmrdir low/high 4h+5 ns t w(tmrclk) pulse duration, tmrclk low as a percentage of tmrclk cycle time 40 60 % t wh(tmrclk) pulse duration, tmrclk high as a percentage of tmrclk cycle time 40 60 % t c(tmrclk) cycle time, tmrclk 4 t c(co) ns 3 parameter tmrdir is equal to the pin tdir, and parameter tmrclk is equal to the pin tclkin. t w(pwm) t d(pwm)co pwmx clkout figure 28. pwm output timing clkout t w(tmrdir) tmrdir figure 29. capture/tmrdir timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 83 post office box 1443 ? houston, texas 772511443 capture and qep timings cap refers to cap1/qep0/iopa3, cap2/qep1/iopa4, and cap3/iopa5. timing requirements [h = 0.5t c(co) ] (see figure 30) min max unit t w(cap) pulse duration, cap input low/high 4h +15 ns capx t w(cap) clkout figure 30. capture input and qep timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 84 post office box 1443 ? houston, texas 772511443 interrupt timings int refers to nmi , xint1, and xint2/io. pdp refers to pdpint . switching characteristics over recommended operating conditions (see figure 31) parameter min max unit t hz(pwm)pdp delay time, pdpint low to pwm to high-impedance state 12 ns t d(int) delay time, int low/high to interrupt-vector fetch 10t c(co) ns timing requirements [h = 0.5t c(co) ] (see figure 31) min max unit t w(int) pulse duration, int input low/high 2h+15 ns t w(pdp) pulse duration, pdpint input low 4h+5 ns pwm pdpint clkout t w(pdp) t hz(pwm)pdp xint1/xint2/nmi t w(int) address interrupt vector t d(int) figure 31. power drive protection interrupt timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 85 post office box 1443 ? houston, texas 772511443 general-purpose input/output timings switching characteristics over recommended operating conditions (see figure 32) parameter min max unit t d(gpo)co delay time clkout low to gpio low/high all gpios 9 ns t d(gpo)co d e l ay ti me, clkout l ow t o gpio l ow /hi g h all gpios 9 ns t r(gpo) rise time, gpio switching low to high all gpios 8 ns t f(gpo) fall time, gpio switching high to low all gpios 6 ns timing requirements [h = 0.5t c(co) ] (see figure 33) min max unit t w(gpi) pulse duration, gpi high/low 2h+15 ns t d(gpo)co gpio clkout t r(gpo) t f(gpo) figure 32. general-purpose output timing gpio clkout t w(gpi) figure 33. general-purpose input timing
tms320f243, tms320f241 dsp controllers s sprs064b december 1997 revised february 1999 t emp l ate r e l ease d ate: 7 11 94 86 post office box 1443 houston, texas 772511443 ? spi master mode timing parameters spi master mode timing information is listed in the following tables. spi master mode external timing parameters (clock phase = 0) 23 (see figure 34) no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit min max min max 1 t c(spc)m cycle time, spiclk 4t c(co) 128t c(co) 5t c(co) 127t c(co) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m 0.5t c(co) 10 0.5t c(spc)m 0.5t c(co) ns 2 t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m 0.5t c(co) 10 0.5t c(spc)m 0.5t c(co) ns 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(co) 10 0.5t c(spc)m + 0.5t c(co) ns 3 t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(co) 10 0.5t c(spc)m + 0.5t c(co) ns 4 t d(spch-simo)m delay time, spiclk high to spisimo valid (clock polarity = 0) 10 10 10 10 ns 4 t d(spcl-simo)m delay time, spiclk low to spisimo valid (clock polarity = 1) 10 10 10 10 ns 5 t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity =0) 0.5t c(spc)m 10 0.5t c(spc)m + 0.5t c(co) 10 ns 5 t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity =1) 0.5t c(spc)m 10 0.5t c(spc)m + 0.5t c(co) 10 ns 8 t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 0) 0 0 ns 8 t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 1) 0 0 ns 9 t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 0) 0.25t c(spc)m 10 0.5t c(spc)m 0.5t c(co) 10 ns 9 t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 1) 0.25t c(spc)m 10 0.5t c(spc)m 0.5t c(co) 10 ns 2 the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is cleared. 3 t c = system clock cycle time = 1/clkout = t c(co) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 87 post office box 1443 ? houston, texas 772511443 parameter measurement information 9 4 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 8 5 3 2 1 spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. figure 34. spi master mode external timing (clock phase = 0)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 t emp l ate r e l ease d ate: 7 11 94 88 post office box 1443 houston, texas 772511443 ? spi master mode external timing parameters (clock phase = 1) 23 (see figure 35) no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit min max min max 1 t c(spc)m cycle time, spiclk 4t c(co) 128t c(co) 5t c(co) 127t c(co) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m 0.5t c(co) 10 0.5t c(spc)m 0.5t c(co) ns 2 t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m 0.5t c(co) 10 0.5t c(spc)m 0.5t c(co) ns 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(co) 10 0.5t c(spc)m + 0.5t c(co) ns 3 t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(co) 10 0.5t c(spc)m + 0.5t c(co) ns 6 t su(simo-spch)m setup time, spisimo data valid before spiclk high (clock polarity = 0) 0.5t c(spc)m 10 0.5t c(spc)m 10 ns 6 t su(simo-spcl)m setup time, spisimo data valid before spiclk low (clock polarity = 1) 0.5t c(spc)m 10 0.5t c(spc)m 10 ns 7 t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity =0) 0.5t c(spc)m 10 0.5t c(spc)m 10 ns 7 t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity =1) 0.5t c(spc)m 10 0.5t c(spc)m 10 ns 10 t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 0) 0 0 ns 10 t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 1) 0 0 ns 11 t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 0) 0.25t c(spc)m 10 0.5t c(spc)m 10 ns 11 t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 1) 0.25t c(spc)m 10 0.5t c(spc)m 10 ns 2 the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is set. 3 t c = system clock cycle time = 1/clkout = t c(co) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 89 post office box 1443 ? houston, texas 772511443 parameter measurement information data valid 11 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 1 7 6 10 3 2 spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. figure 35. spi master mode external timing (clock phase = 1)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 90 post office box 1443 ? houston, texas 772511443 spi slave mode timing parameters slave mode timing information is listed in the following tables. spi slave mode external timing parameters (clock phase = 0) 23 (see figure 36) no. min max unit 12 t c(spc)s cycle time, spiclk 4t c(co) 3 ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s 10 0.5t c(spc)s ns 13 t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s 10 0.5t c(spc)s ns 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s 10 0.5t c(spc)s ns 14 t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s 10 0.5t c(spc)s ns 15 t d(spch-somi)s delay time, spiclk high to spisomi valid (clock polarity = 0) 0.375t c(spc)s 10 ns t d(spcl-somi)s delay time, spiclk low to spisomi valid (clock polarity = 1) 0.375t c(spc)s 10 16 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =0) 0.75t c(spc)s ns 16 t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =1) 0.75t c(spc)s ns 19 t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 0) 0 ns 19 t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 1) 0 ns 20 t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)s ns 20 t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)s ns 2 the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is cleared. 3 t c = system clock cycle time = 1/clkout = t c(co) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 91 post office box 1443 ? houston, texas 772511443 parameter measurement information 20 15 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 19 16 14 13 12 spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. figure 36. spi slave mode external timing (clock phase = 0)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 92 post office box 1443 ? houston, texas 772511443 spi slave mode external timing parameters (clock phase = 1) 23 (see figure 37) no. min max unit 12 t c(spc)s cycle time, spiclk 8t c(co) ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s 10 0.5t c(spc)s ns 13 t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s 10 0.5t c(spc)s ns 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s 10 0.5t c(spc)s ns 14 t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s 10 0.5t c(spc)s ns 17 t su(somi-spch)s setup time, spisomi before spiclk high (clock polarity = 0) 0.125t c(spc)s ns 17 t su(somi-spcl)s setup time, spisomi before spiclk low (clock polarity = 1) 0.125t c(spc)s ns 18 t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =0) 0.75t c(spc)s ns 18 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =1) 0.75t c(spc)s ns 21 t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 0) 0 ns 21 t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 1) 0 ns 22 t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)s ns 22 t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)s ns 2 the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is set. 3 t c = system clock cycle time = 1/clkout = t c(co) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 93 post office box 1443 ? houston, texas 772511443 parameter measurement information data valid 22 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 21 12 18 17 14 13 spiste 2 2 the spiste signal must be active before the spi communication stream starts; the spiste signal must remain active until the spi communication stream is complete. figure 37. spi slave mode external timing (clock phase = 1)
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 94 post office box 1443 ? houston, texas 772511443 external memory interface read timings switching characteristics over recommended operating conditions for an external memory interface read (see figure 38) parameter min max unit t d(colcntl) delay time, clkout low to control valid 3 ns t d(colcnth) delay time, clkout low to control inactive 3 ns t d(cola)rd delay time, clkout low to address valid 5 ns t d(cohrdl) delay time, clkout high to rd strobe active 4 ns t d(colrdh) delay time, clkout low to rd strobe inactive high 4 0 ns t d(colsl) delay time, clkout low to strb strobe active low 3 ns t d(colsh) delay time, clkout low to strb strobe inactive high 3 ns t h(a)col hold time, address valid after clkout low 4 ns t su(a)rd setup time, address valid before rd strobe active low 22 ns t h(a)rd hold time, address valid after rd strobe inactive high 1 ns timing requirements [h = 0.5t c(co) ] (see figure 38) min max unit t a(a) access time, read data from address valid 2h20 ns t su(d)rd setup time, read data before rd strobe inactive high 12 ns t h(d)rd hold time, read data after rd strobe inactive high 0 ns t h(aiv-d) hold time, read data after address invalid 3 ns
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 95 post office box 1443 ? houston, texas 772511443 external memory interface read timings (continued) t d(colcnth) t h(a)col t d(cola)rd t h(a)col t d(colrdh) t d(cohrdl) t a(a) t d(cohrdl) clkout ps , ds , is , br a[0:15] t d(colcntl) t d(cola)rd t h(a)rd t su(d)rd t h(d)rd t su(a)rd t h(d)rd t su(d)rd t d(colsh) rd d[0:15] strb t d(colsl) t d(colrdh) t a(a) t h(aivd) figure 38. memory interface read/read timings
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 96 post office box 1443 ? houston, texas 772511443 external memory interface write timings switching characteristics over recommended operating conditions for an external memory interface write [h = 0.5t c(co) ] (see figure 39) parameter min max unit t d(cohcntl) delay time, clkout high to control valid 9 ns t d(cohcnth) delay time, clkout high to control inactive 9 ns t d(coha)w delay time, clkout high to address valid 11 ns t d(cohrwl) delay time, clkout high to r/w low 6 ns t d(cohrwh) delay time, clkout high to r/w high 6 ns t d(colwl) delay time, clkout low to we strobe active low 4 0 ns t d(colwh) delay time, clkout low to we strobe inactive high 4 0 ns t en(d)col enable time, data bus driven from clkout low 7 ns t d(colsl) delay time, clkout low to strb active low 3 ns t d(colsh) delay time, clkout low to strb inactive high 3 ns t h(a)cohw hold time, address valid after clkout high h1 ns t su(a)w setup time, address valid before we strobe active low h9 ns t su(d)w setup time, write data before we strobe inactive high 2h1 ns t h(d)w hold time, write data after we strobe inactive high 3 ns t dis(w-d) disable time, data bus high impedance from we high 4 ns
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 97 post office box 1443 ? houston, texas 772511443 external memory interface write timings (continued) t dis(w-d) t d(coha)w t d(cohrwl) t su(a)w t d(colwh) we strb t en(d)col t d(colwl) t h(a)cohw t d(cohcntl) t d(cohcnth) clkout a[0:15] r/w ps , ds , is , br t d(cohcntl) t d(cohrwh) t d(colwl) t d(colwh) t h(d)w t su(d)w t en(d)col t d(colsh) vis_clk ena_144 vis_oe t h(d)w 2h 2h t d(colsl) note a: ena_144 when active low along with bvis bits (10,9 set to 01 or 11) in register wsgr - io@ffffh, vis_clk and vis_oe will be visible at pins 31 ('f243) and 126 ('f243) respectively. vis_clk and vis_oe indicate internal memory write cycles (program/data). during vis_oe cycles, the external bus will be driven. vis_clk is essentially clkout, to be used along with vis_oe for trace capabilities. t su(d)w t d(colsl) d[0:15] t d(colsh) figure 39. address visibility mode
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 98 post office box 1443 ? houston, texas 772511443 external memory interface ready-on-read timings switching characteristics over recommended operating conditions for an external memory interface ready-on-read (see figure 40) parameter min max unit t d(cola)rd delay time, clkout low to address valid 5 ns timing requirements for an external memory interface ready-on-read (see figure 40) min max unit t h(rdy)coh hold time, ready after clkout high 5 ns t su(d)rd setup time, read data before rd strobe inactive high 12 ns t v(rdy)ard valid time, ready after address valid on read 4 ns t su(rdy)coh setup time, ready before clkout high 17 ns t h(rdy)coh clkout ps , ds , is , br rd d[0:15] strb a[0:15] t d(cola)rd t v(rdy)ard t su ( rdy ) coh ready wait cycle t su(d)rd figure 40. ready-on-read timings
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 99 post office box 1443 ? houston, texas 772511443 external memory interface ready-on-write timings switching characteristics over recommended operating conditions for an external memory interface ready-on-write (see figure 41) parameter min max unit t d(coha)w delay time, clkout high to address valid 11 ns timing requirements for an external memory interface ready-on-write [h = 0.5t c(co) ] (see figure 41) min max unit t h(rdy)coh hold time, ready after clkout high 5 ns t su(d)w setup time, write data before we strobe inactive high 2h1 2h ns t v(rdy)aw valid time, ready after address valid on write 4 ns t su(rdy)coh setup time, ready before clkout high 17 ns t su(d)w clkout ps , ds , is , br t d(coha)w a[0:15] we d[0:15] strb t su(rdy)coh t h(rdy)coh ready t v(rdy)aw wait cycle figure 41. ready-on-write timings
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 100 post office box 1443 ? houston, texas 772511443 10-bit dual analog-to-digital converter (adc) the 10-bit adc has a separate power bus for its analog circuitry. these pins are referred to as v cca and v ssa . the power bus isolation is to enhance adc performance by preventing digital switching noise of the logic circuitry that can be present on v ss and v cc from coupling into the adc analog stage. all adc specifications are given with respect to v ssa unless otherwise noted. resolution 10-bit (1024 values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . monotonic assured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output conversion mode 000h to 3ffh (000h for v i v ssa ; 3ffh for v i v cca ) . . . . . . . . . . . . . . . . . . . . . . . conversion time (including sample time) 1 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions min nom max unit v cca analog supply voltage 4.5 5 5.5 v v ssa analog ground 0 v v refhi analog supply reference source 2 v reflo v cca v v reflo analog ground reference source 2 v ssa v refhi v v ai analog input voltage, adcin00adcin07 v ssa v cca v 2 v refhi and v reflo must be stable, within 1/2 lsb of the required resolution, during the entire conversion time. adc operating frequency min max unit adc operating frequency 20 mhz
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 101 post office box 1443 ? houston, texas 772511443 operating characteristics over recommended operating condition ranges 2 parameter description min max unit v cca =55v converting 10 ma i cca analog su pp ly current v cca = 5 . 5 v non-converting 2 ma i cca analog su ly current v cca = v refhi = 5.5 v pll or osc power down 1 a c i analog in p ut ca p acitance typical capacitive load on non-sampling 10 p f c ai analog inp u t capacitance y analog input pin sampling 30 pf e dnl differential nonlinearity error difference between the actual step width and the ideal value 2 lsb e inl integral nonlinearity error maximum deviation from the best straight line through the adc transfer characteristics, excluding the quantization error 2 lsb t d(pu) delay time, power-up to adc valid time to stabilize analog stage after power-up 10 s z ai analog input source impedance analog input source impedance for conversions to remain within specifications 10 w 2 absolute resolution = 4.89 mv. at v refhi = 5 v and v reflo = 0 v, this is one lsb. as v refhi decreases, v reflo increases, or both, the lsb size decreases. therefore, the absolute accuracy and differential/integral linearity errors in terms of lsbs increase. adc input pin circuit one of the most common a/d application errors is inappropriate source impedance. in practice, minimum source impedance should be used to limit the error as well as to minimize the required sampling time; however, the source impedance must be smaller than z ai . a typical adc input pin circuit is shown in figure 42. v in r1 r equiv v ai (to adcinx input) r1 = 10 w typical figure 42. typical adc input pin circuit
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 102 post office box 1443 ? houston, texas 772511443 internal adc module timings (see figure 43) min max unit t c(ad) cycle time, adc prescaled clock 50 ns t w(shc) pulse duration, total sample/hold and conversion time 2 900 ns t w(sh) pulse duration, sample and hold time 3t c(ad) ns t w(c) pulse duration, total conversion time 10t c(ad) ns t d(soc-sh) delay time, start of conversion 3 to beginning of sample and hold 3t c(co) ns t d(eoc-fifo) delay time, end of conversion to data loaded into result fifo 2t c(co) ns t d(adcint) delay time, adc flag to adc interrupt 2t c(co) ns 2 the total sample/hold and conversion time is determined by the summation of t d(soc-sh) , t w(sh ), t w(c) , and t d(eoc-fifo) . 3 start of conversion is signaled by the adcimstart bit (adctrl1.13) or the adcsoc bit (adctrl1.0) set in software, the external start signal active (adcsoc), or internal evsoc signal active. 0 3 2 4 51 t w(c) 6 7 8 t c(ad) adc clock analog input bit converted t d(socsh) eoc/convert internal start/ sample hold start of convert xfr to fifo t w(shc) t d(eocfifo) 9 t w(sh) t d(adcint) figure 43. analog-to-digital internal module timing
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 103 post office box 1443 ? houston, texas 772511443 flash eeprom switching characteristics over recommended operating conditions parameter 'f243/'f241 unit parameter min typ max unit program-erase endurance 10k cycles program pulses per word 2 1 10 150 pulses erase pulses per array 2 1 20 1000 pulses flash-write pulses per array 2 1 20 6000 pulses 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/tms320f24x dsp embedded flash memory technical reference (literature number spru282). timing requirements 'f243/'f241 unit min max unit t d(busy) delay time, after mode deselect to stabilization 2 10 m s t d(rd-verify) delay time, verify read mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/tms320f24x dsp embedded flash memory technical reference (literature number spru282). programming operation parameter 'f243/'f241 unit parameter min nom max unit t w(pgm) pulse duration, programming algorithm 2 95 100 105 m s t d(pgm-mode) delay time, program mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/tms320f24x dsp embedded flash memory technical reference (literature number spru282). erase operation parameter 'f243/'f241 unit parameter min nom max unit t w(erase) pulse duration, erase algorithm 2 6.65 7 7.35 ms t d(erase-mode) delay time, erase mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/tms320f24x dsp embedded flash memory technical reference (literature number spru282). flash-write operation parameter 'f243/'f241 unit parameter min nom max unit t w(flw) pulse duration, flash-write algorithm 2 13.3 14 14.7 ms t d(flw-mode) delay time, flash-write mode select to stabilization 2 10 m s 2 these parameters are used in the flash programming algorithms. for a detailed description of the algorithms, see the tms320f20x/tms320f24x dsp embedded flash memory technical reference (literature number spru282).
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 104 post office box 1443 ? houston, texas 772511443 register file compilation table 24 is a collection of all the programmable registers of the tms320x24x (provided for a quick reference). table 24. register file compilation addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data memory space cpu status registers arp ov ovm 1 intm dp(8) st0 dp(7) dp(6) dp(5) dp(4) dp(3) dp(2) dp(1) dp(0) st0 arb cnf tc sxm c 1 st1 1 1 1 xf 1 1 pm st1 global memory and cpu interrupt registers 00004h e e e e e e e e imr 00004h e e int6 mask int5 mask int4 mask int3 mask int2 mask int1 mask imr 00005h e e e e e e e e greg 00005h global data memory configuration bits (70) greg 00006h e e e e e e e e ifr 00006h e e int6 flag int5 flag int4 flag int3 flag int2 flag int1 flag ifr system registers 07010h irq0.15 irq0.14 irq0.13 irq0.12 irq0.11 irq0.10 irq0.9 irq0.8 pirqr0 07010h irq0.7 irq0.6 irq0.5 irq0.4 irq0.3 irq0.2 irq0.1 irq0.0 pirqr0 07011h irq1.15 irq1.14 irq1.13 irq1.12 irq1.11 irq1.10 irq1.9 irq1.8 pirqr1 07011h irq1.7 irq1.6 irq1.5 irq1.4 irq1.3 irq1.2 irq1.1 irq1.0 pirqr1 07012h to 07013h reserved 07014h iak0.15 iak0.14 iak0.13 iak0.12 iak0.11 iak0.10 iak0.9 iak0.8 piackr0 07014h iak0.7 iak0.6 iak0.5 iak0.4 iak0.3 iak0.2 iak0.1 iak0.0 piackr0 07015h iak1.15 iak1.14 iak1.13 iak1.12 iak1.11 iak1.10 iak1.9 iak1.8 piackr1 07015h iak1.7 iak1.6 iak1.5 iak1.4 iak1.3 iak1.2 iak1.1 iak1.0 piackr1 07016h to 07017h reserved 07018h e clksrc lpm1 lpm0 e e e e scsr 07018h e e e e e e e illadr scsr 07019h to 0701bh reserved 0701ch din15 din14 din13 din12 din11 din10 din9 din8 dinr 0701ch din7 din6 din5 din4 din3 din2 din1 din0 dinr 0701dh reserved 0701eh v15 v14 v13 v12 v11 v10 v9 v8 pivr 0701eh v7 v6 v5 v4 v3 v2 v1 v0 pivr 0701fh reserved
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 105 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wd control registers 07020h to 07022h reserved 07023h d7 d6 d5 d4 d3 d2 d1 d0 wdcntr 07024h reserved 07025h d7 d6 d5 d4 d3 d2 d1 d0 wdkey 07026h to 07028h reserved 07029h wd flag wddis wdchk2 wdchk1 wdchk0 wdps2 wdps1 wdps0 wdcr 0702ah to 0702ch reserved 0702dh to 07031h reserved a-to-d module control registers 07032h suspend- soft suspend- free adcim- start adc2en adc1en adccon- run adcinten adcintflag adctrl1 adceoc adc2chsel adc1chsel adcsoc 07033h reserved 07034h e e evsocp extsocp intpri adcevsoc adcextsoc e adctrl2 07034h adcfifo2 e adcfifo1 adcpscale adctrl2 07035h reserved 07036h d9 d8 d7 d6 d5 d4 d3 d2 adcfifo1 07036h d1 d0 0 0 0 0 0 0 adcfifo1 07037h reserved 07038h d9 d8 d7 d6 d5 d4 d3 d2 adcfifo2 07038h d1 d0 0 0 0 0 0 0 adcfifo2 07039h to 0703fh reserved serial peripheral interface (spi) configuration control registers 07040h spi sw reset clock polarity e e spi char3 spi char2 spi char1 spi char0 spiccr 07041h e e e overrun int ena clock phase master/ slave talk spi int ena spictl 07042h receiver overrun flag spi int flag tx buf full flag e e e e e spists 07043h reserved 07044h e spi bit rate 6 spi bit rate 5 spi bit rate 4 spi bit rate 3 spi bit rate 2 spi bit rate 1 spi bit rate 0 spibrr 07045h reserved 07046h erxb15 erxb14 erxb13 erxb12 erxb11 erxb10 erxb9 erxb8 spirxemu 07046h erxb7 erxb6 erxb5 erxb4 erxb3 erxb2 erxb1 erxb0 spirxemu
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 106 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 serial peripheral interface (spi) configuration control registers (continued) 07047h rxb15 rxb14 rxb13 rxb12 rxb11 rxb10 rxb9 rxb8 spirxbuf 07047h rxb7 rxb6 rxb5 rxb4 rxb3 rxb2 rxb1 rxb0 spirxbuf 07048h txb15 txb14 txb13 txb12 txb11 txb10 txb9 txb8 spitxbuf 07048h txb7 txb6 txb5 txb4 txb3 txb2 txb1 txb0 spitxbuf 07049h sdat15 sdat14 sdat13 sdat12 sdat11 sdat10 sdat9 sdat8 spidat 07049h sdat7 sdat6 sdat5 sdat4 sdat3 sdat2 sdat1 sdat0 spidat 0704ah reserved 0704eh 0704fh e spi priority spi susp soft spi susp free e e e e spipri serial communications interface (sci) configuration control registers 07050h stop bits even/odd parity parity enable loop back ena addr/idle mode sci char2 sci char1 sci char0 sciccr 07051h e rx err int ena sw reset e txwake sleep txena rxena scictl1 07052h baud15 (msb) baud14 baud13 baud12 baud11 baud10 baud9 baud8 scihbaud 07053h baud7 baud6 baud5 baud4 baud3 baud2 baud1 baud0 (lsb) scilbaud 07054h txrdy tx empty e e e e rx/bk int ena tx int ena scictl2 07055h rx error rxrdy brkdt fe oe pe rxwake e scirxst 07056h erxdt7 erxdt6 erxdt5 erxdt4 erxdt3 erxdt2 erxdt1 erxdt0 scirxemu 07057h rxdt7 rxdt6 rxdt5 rxdt4 rxdt3 rxdt2 rxdt1 rxdt0 scirxbuf 07058h reserved 07059h txdt7 txdt6 txdt5 txdt4 txdt3 txdt2 txdt1 txdt0 scitxbuf 0705ah to 0705eh reserved 0705fh e scitx priority scirx priority sci soft sci free e e e scipri 07060h to 0706fh reserved external interrupt control registers 07070h xint1 flag e e e e e e e xint1cr 07070h e e e e e xint1 polarity xint1 priority xint1 ena xint1cr 07071h xint2 flag e e e e e e e xint2cr 07071h e e e e e xint2 polarity xint2 priority xint2 ena xint2cr
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 107 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 external interrupt control registers (continued) 07072h to 0708fh reserved digital i/o control registers 07090h cra.15 cra.14 cra.13 cra.12 cra.11 cra.10 cra.9 cra.8 ocra 07090h cra.7 cra.6 cra.5 cra.4 cra.3 cra.2 cra.1 cra.0 ocra 07091h reserved 07092h e e e e e e crb.9 crb.8 ocrb 07092h crb.7 crb.6 crb.5 crb.4 crb.3 crb.2 crb.1 crb.0 ocrb 07093h to 07097h reserved 07098h a7dir a6dir a5dir a4dir a3dir a2dir a1dir a0dir padatdir 07098h iopa7 iopa6 iopa5 iopa4 iopa3 iopa2 iopa1 iopa0 padatdir 07099h reserved 0709ah b7dir b6dir b5dir b4dir b3dir b2dir b1dir b0dir pbdatdir 0709ah iopb7 iopb6 iopb5 iopb4 iopb3 iopb2 iopb1 iopb0 pbdatdir 0709bh reserved 0709ch c7dir c6dir c5dir c4dir c3dir c2dir c1dir c0dir pcdatdir 0709ch iopc7 iopc6 iopc5 iopc4 iopc3 iopc2 iopc1 iopc0 pcdatdir 0709dh reserved 0709eh d7dir d6dir d5dir d4dir d3dir d2dir d1dir d0dir pddatdir 0709eh iopd7 iopd6 iopd5 iopd4 iopd3 iopd2 iopd1 iopd0 pddatdir 0709fh reserved controller area network (can) configuration control registers 07100h e e e e e e e e mder 07100h md3 md2 me5 me4 me3 me2 me1 me0 mder 07101h ta5 ta4 ta3 ta2 aa5 aa4 aa3 aa2 tcr 07101h trs5 trs4 trs3 trs2 trr5 trr4 trr3 trr2 tcr 07102h rfp3 rfp2 rfp1 rfp0 rml3 rml2 rml1 rml0 rcr 07102h rmp3 rmp2 rmp1 rmp0 opc3 opc2 opc1 opc0 rcr 07103h e e susp ccr pdr dbo wuba cdr mcr 07103h abo stm e e e e mbnr1 mbnr0 mcr 07104h e e e e e e e e bcr2 07104h brp7 brp6 brp5 brp4 brp3 brp2 brp1 brp0 bcr2 07105h e e e e e sbg sjw1 sjw0 bcr1 07105h sam tseg13 tseg12 tseg11 tseg10 tseg22 tseg21 tseg20 bcr1 07106h e e e e e e e fer esr 07106h bef sa1 crce ser acke bo ep ew esr 07107h e e e e e e e e gsr 07107h e e sma cce pda e rm tm gsr 07108h tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 cec 07108h rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 cec
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 108 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 controller area network (can) configuration control registers (continued) 07109h e e mif5 mif4 mif3 mif2 mif1 mif0 can ifr 07109h e rmlif aaif wdif wuif boif epif wlif can _ ifr 0710ah mil e mim5 mim4 mim3 mim2 mim1 mim0 can imr 0710ah eil rmlim aaim wdim wuim boim epim wlim can _ imr 0710bh lami e e lam028 lam027 lam026 lam025 lam024 lam0 h 0710bh lam023 lam022 lam021 lam020 lam019 lam018 lam017 lam016 lam0 _ h 0710ch lam015 lam014 lam013 lam012 lam011 lam010 lam09 lam08 lam0 l 0710ch lam07 lam06 lam05 lam04 lam03 lam02 lam01 lam00 lam0 _ l 0710dh lami e e lam128 lam127 lam126 lam125 lam124 lam1 h 0710dh lam123 lam122 lam121 lam120 lam119 lam118 lam117 lam116 lam1 _ h 0710eh lam115 lam114 lam113 lam112 lam111 lam110 lam19 lam18 lam1 l 0710eh lam17 lam16 lam15 lam14 lam13 lam12 lam11 lam10 lam1 _ l 0710fh to 071ffh reserved message object #0 07200h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid0l 07200h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid0l 07201h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid0h 07201h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid0h 07202h e e e e e e e e msgctrl0 07202h e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl0 07203h reserved 07204h d15 d14 d13 d12 d11 d10 d9 d8 mbx0a 07204h d7 d6 d5 d4 d3 d2 d1 d0 mbx0a 07205h d15 d14 d13 d12 d11 d10 d9 d8 mbx0b 07205h d7 d6 d5 d4 d3 d2 d1 d0 mbx0b 07206h d15 d14 d13 d12 d11 d10 d9 d8 mbx0c 07206h d7 d6 d5 d4 d3 d2 d1 d0 mbx0c 07207h d15 d14 d13 d12 d11 d10 d9 d8 mbx0d 07207h d7 d6 d5 d4 d3 d2 d1 d0 mbx0d message object #1 07208h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid1l 07208h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid1l 07209h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid1h 07209h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid1h 0720ah e e e e e e e e msgctrl1 0720ah e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl1 0720bh reserved 0720ch d15 d14 d13 d12 d11 d10 d9 d8 mbx1a 0720ch d7 d6 d5 d4 d3 d2 d1 d0 mbx1a 0720dh d15 d14 d13 d12 d11 d10 d9 d8 mbx1b 0720dh d7 d6 d5 d4 d3 d2 d1 d0 mbx1b
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 109 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 controller area network (can) configuration control registers (continued) 0720eh d15 d14 d13 d12 d11 d10 d9 d8 mbx1c 0720eh d7 d6 d5 d4 d3 d2 d1 d0 mbx1c 0720fh d15 d14 d13 d12 d11 d10 d9 d8 mbx1d 0720fh d7 d6 d5 d4 d3 d2 d1 d0 mbx1d message object #2 07210h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid2l 07210h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid2l 07211h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid2h 07211h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid2h 07212h e e e e e e e e msgctrl2 07212h e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl2 07213h reserved 07214h d15 d14 d13 d12 d11 d10 d9 d8 mbx2a 07214h d7 d6 d5 d4 d3 d2 d1 d0 mbx2a 07215h d15 d14 d13 d12 d11 d10 d9 d8 mbx2b 07215h d7 d6 d5 d4 d3 d2 d1 d0 mbx2b 07216h d15 d14 d13 d12 d11 d10 d9 d8 mbx2c 07216h d7 d6 d5 d4 d3 d2 d1 d0 mbx2c 07217h d15 d14 d13 d12 d11 d10 d9 d8 mbx2d 07217h d7 d6 d5 d4 d3 d2 d1 d0 mbx2d message object #3 07218h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid3l 07218h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid3l 07219h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid3h 07219h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid3h 0721ah e e e e e e e e msgctrl3 0721ah e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl3 0721bh reserved 0721ch d15 d14 d13 d12 d11 d10 d9 d8 mbx3a 0721ch d7 d6 d5 d4 d3 d2 d1 d0 mbx3a 0721dh d15 d14 d13 d12 d11 d10 d9 d8 mbx3b 0721dh d7 d6 d5 d4 d3 d2 d1 d0 mbx3b 0721eh d15 d14 d13 d12 d11 d10 d9 d8 mbx3c 0721eh d7 d6 d5 d4 d3 d2 d1 d0 mbx3c 0721fh d15 d14 d13 d12 d11 d10 d9 d8 mbx3d 0721fh d7 d6 d5 d4 d3 d2 d1 d0 mbx3d message object #4 07220h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid4l 07220h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid4l 07221h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid4h 07221h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid4h
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 110 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 controller area network (can) configuration control registers (continued) 07222h e e e e e e e e msgctrl4 07222h e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl4 07223h reserved 07224h d15 d14 d13 d12 d11 d10 d9 d8 mbx4a 07224h d7 d6 d5 d4 d3 d2 d1 d0 mbx4a 07225h d15 d14 d13 d12 d11 d10 d9 d8 mbx4b 07225h d7 d6 d5 d4 d3 d2 d1 d0 mbx4b 07226h d15 d14 d13 d12 d11 d10 d9 d8 mbx4c 07226h d7 d6 d5 d4 d3 d2 d1 d0 mbx4c 07227h d15 d14 d13 d12 d11 d10 d9 d8 mbx4d 07227h d7 d6 d5 d4 d3 d2 d1 d0 mbx4d message object #5 07228h idl15 idl14 idl13 idl12 idl11 idl10 idl9 idl8 msgid5l 07228h idl7 idl6 idl5 idl4 idl3 idl2 idl1 idl0 msgid5l 07229h ide ame aam idh28 idh27 idh26 idh25 idh24 msgid5h 07229h idh23 idh22 idh21 idh20 idh19 idh18 idh17 idh16 msgid5h 0722ah e e e e e e e e msgctrl5 0722ah e e e rtr dlc3 dlc2 dlc1 dlc0 msgctrl5 0722bh reserved 0722ch d15 d14 d13 d12 d11 d10 d9 d8 mbx5a 0722ch d7 d6 d5 d4 d3 d2 d1 d0 mbx5a 0722dh d15 d14 d13 d12 d11 d10 d9 d8 mbx5b 0722dh d7 d6 d5 d4 d3 d2 d1 d0 mbx5b 0722eh d15 d14 d13 d12 d11 d10 d9 d8 mbx5c 0722eh d7 d6 d5 d4 d3 d2 d1 d0 mbx5c 0722fh d15 d14 d13 d12 d11 d10 d9 d8 mbx5d 0722fh d7 d6 d5 d4 d3 d2 d1 d0 mbx5d 07230h to 073ffh reserved general-purpose (gp) timer configuration control registers 07400h e t2stat t1stat e t2toadc t1toadc(1) gptcon 07400h t1toadc(0) tcompoe e t2pin t1pin gptcon 07401h d15 d14 d13 d12 d11 d10 d9 d8 t1cnt 07401h d7 d6 d5 d4 d3 d2 d1 d0 t1cnt 07402h d15 d14 d13 d12 d11 d10 d9 d8 t1cmpr 07402h d7 d6 d5 d4 d3 d2 d1 d0 t1cmpr 07403h d15 d14 d13 d12 d11 d10 d9 d8 t1pr 07403h d7 d6 d5 d4 d3 d2 d1 d0 t1pr 07404h free soft e tmode1 tmode0 tps2 tps1 tps0 t1con 07404h tswt1 tenable tclks1 tclks0 tcld1 tcld0 tecmpr selt1pr t1con 07405h d15 d14 d13 d12 d11 d10 d9 d8 t2cnt 07405h d7 d6 d5 d4 d3 d2 d1 d0 t2cnt
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 111 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general-purpose (gp) timer configuration control registers (continued) 07406h d15 d14 d13 d12 d11 d10 d9 d8 t2cmpr 07406h d7 d6 d5 d4 d3 d2 d1 d0 t2cmpr 07407h d15 d14 d13 d12 d11 d10 d9 d8 t2pr 07407h d7 d6 d5 d4 d3 d2 d1 d0 t2pr 07408h free soft e tmode1 tmode0 tps2 tps1 tps0 t2con 07408h tswt1 tenable tclks1 tclks0 tcld1 tcld0 tecmpr selt1pr t2con 07409h to 07410h reserved full and simple compare unit registers 07411h cenable cld1 cld0 svenable actrld1 actrld0 fcompoe e comcon 07411h e e e e e e e e comcon 07412h reserved 07413h svrdir d2 d1 d0 cmp6act1 cmp6act0 cmp5act1 cmp5act0 actr 07413h cmp4act1 cmp4act0 cmp3act1 cmp3act0 cmp2act1 cmp2act0 cmp1act1 cmp1act0 actr 07414h reserved 07414h r eserve d 07415h e e e e dbt3 dbt2 dbt1 dbt0 dbtcon 07415h edbt3 edbt2 edbt1 dbtps2 dbtps1 dbtps0 e e dbtcon 07416h reserved 07417h d15 d14 d13 d12 d11 d10 d9 d8 cmpr1 07417h d7 d6 d5 d4 d3 d2 d1 d0 cmpr1 07418h d15 d14 d13 d12 d11 d10 d9 d8 cmpr2 07418h d7 d6 d5 d4 d3 d2 d1 d0 cmpr2 07419h d15 d14 d13 d12 d11 d10 d9 d8 cmpr3 07419h d7 d6 d5 d4 d3 d2 d1 d0 cmpr3 0741ah to 0741fh reserved capture unit registers 07420h capres capqepn cap3en e cap3tsel cap12tsel cap3toadc capcon 07420h cap1edge cap2edge cap3edge e capcon 07421h reserved 07422h e cap3fifo cap2fifo cap1fifo capfifo 07422h e e e e e e e e capfifo 07423h d15 d14 d13 d12 d11 d10 d9 d8 cap1fifo 07423h d7 d6 d5 d4 d3 d2 d1 d0 cap1fifo 07424h d15 d14 d13 d12 d11 d10 d9 d8 cap2fifo 07424h d7 d6 d5 d4 d3 d2 d1 d0 cap2fifo 07425h d15 d14 d13 d12 d11 d10 d9 d8 cap3fifo 07425h d7 d6 d5 d4 d3 d2 d1 d0 cap3fifo 07426h reserved
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 112 post office box 1443 ? houston, texas 772511443 register file compilation (continued) table 24. register file compilation (continued) addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 capture unit registers (continued) 07427h d15 d14 d13 d12 d11 d10 d9 d8 cap1fbot 07427h d7 d6 d5 d4 d3 d2 d1 d0 cap1fbot 07428h d15 d14 d13 d12 d11 d10 d9 d8 cap2fbot 07428h d7 d6 d5 d4 d3 d2 d1 d0 cap2fbot 07429h d15 d14 d13 d12 d11 d10 d9 d8 cap3fbot 07429h d7 d6 d5 d4 d3 d2 d1 d0 cap3fbot 0742ah to 0742bh reserved event manager (ev) interrupt control registers 0742ch e e e e e t1ofint ena t1ufint ena t1cint ena evimra 0742ch t1pint ena e e e cmp3int ena cmp2int ena cmp1int ena pdpint ena evimra e e e e e e e e 0742dh e e e e t2ofint ena t2ufint ena t2cint ena t2pint ena evimrb e e e e e e e e 0742eh e e e e e cap3int ena cap2int ena cap1int ena evimrc 0742fh e e e e e t1ofint flag t1ufint flag t1cint flag evifra 0742fh t1pint flag e e e cmp3int flag cmp2int flag cmp1int flag pdpint flag evifra e e e e e e e e 07430h e e e e t2ofint flag t2ufint flag t2cint flag t2pint flag evifrb e e e e e e e e 07431h e e e e e cap3int flag cap2int flag cap1int flag evifrc 07432h to 0743fh reserved i/o memory space flash control mode register ff0fh e e e e e e e e fcmr ff0fh e e e e e e e e fcmr wait-state generator control register 0ffffh e e e e e bvis.1 bvis.0 isws.2 wsgr 0ffffh isws.1 isws.0 dsws.2 dsws.1 dsws.0 psws.2 psws.1 psws.0 wsgr
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 113 post office box 1443 ? houston, texas 772511443 mechanical data pge (s-pqfp-g144) plastic quad flatpack 4040147 / c 11/96 0,27 72 0,17 37 73 0,13 nom 0,25 0,75 0,45 0,05 min 36 seating plane gage plane 108 109 144 sq sq 22,20 21,80 1 19,80 17,50 typ 20,20 1,35 1,45 1,60 max m 0,08 0 7 0,08 0,50 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 typical thermal resistance characteristics parameter description c/w q ja junction-to-ambient 35 q jc junction-to-case 8.5
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 114 post office box 1443 ? houston, texas 772511443 mechanical data fn (s-pqcc-j**) plastic j-leaded chip carrier 4040005 / b 03/95 20 pin shown 0.026 (0,66) 0.032 (0,81) d2 / e2 0.020 (0,51) min 0.180 (4,57) max 0.120 (3,05) 0.090 (2,29) d2 / e2 0.013 (0,33) 0.021 (0,53) seating plane max d2 / e2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) max 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) nom 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) min 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) 18 19 14 13 d d1 1 3 9 e1 e 4 8 min max min pins ** 20 28 44 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 52 68 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) d/e 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) no. of d1 / e1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) m 0.007 (0,18) 0.050 (1,27) notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-018 typical thermal resistance characteristics parameter description c/w q ja junction-to-ambient 48 q jc junction-to-case 11
tms320f243, tms320f241 dsp controllers sprs064b december 1997 revised february 1999 115 post office box 1443 ? houston, texas 772511443 mechanical data pg (r-pqfp-g64) plastic quad flatpack 4040101 / b 03/95 0,15 nom 18,00 14,20 13,80 17,20 32 33 20 19 12,00 typ 0,25 1,10 0,70 0,10 min gage plane 51 1 18,00 typ 52 64 23,60 24,40 19,80 20,20 3,10 max 2,70 typ 0,25 0,45 0 10 seating plane 0,10 1,00 m 0,20 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. contact field sales office to determine if a tighter coplanarity requirement is available for this package. typical thermal resistance characteristics parameter description c/w q ja junction-to-ambient 35 q jc junction-to-case 11
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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